Nanorod DRAM Cells Reduce Leakage via Band Gap Engineering
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the size of DRAM devices while minimizing channel leakage currents, as scaling down MOSFETs leads to increased channel resistance and leakage, necessitating alternative mechanisms for reducing cell geometry.
Innovation Solution
The use of semiconductor nanorods with reduced diameters to increase the band gap energy, reducing leakage currents and improving carrier transport properties by shifting from a three-dimensional to a two-dimensional density of states, and employing a stacked capacitor-transistor arrangement with a gate dielectric to enhance capacitance without increasing area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MOSFET channel length is scaled down to reduce device size, then device density increases, but channel leakage current increases
Solution Approach 1:
The patent changes the fundamental parameter of the channel structure from planar to vertical nanorod geometry. This dimensional transformation maintains electrical performance while enabling significant reduction in device footprint, directly addressing the contradiction between device size reduction and leakage current control
Solution Approach 2:
The invention transitions from two-dimensional planar MOSFET channels to three-dimensional vertical nanorod channels. This dimensional change allows the channel to extend vertically through the substrate, achieving high device density while maintaining effective gate control and low leakage currents through the narrow rod geometry
2Object-generated harmful factors
If nanorod diameter is reduced to increase band gap energy, then leakage current decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned fabrication processes where subsequent fabrication steps automatically align to previously formed structures. This self-service approach minimizes the accumulation of alignment errors and reduces the stringency of precision requirements, enabling the formation of narrow nanorods with controlled diameters
Solution Approach 2:
The fabrication process performs preliminary actions by first forming sacrificial structures and alignment markers before creating the nanorods. This preliminary preparation establishes precise geometric constraints that guide subsequent nanorod formation, ensuring consistent diameter control without requiring extreme precision in every step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower leakage currents, faster switching speeds, and improved charge retention in DRAM cells, enabling smaller device sizes with maintained performance characteristics.
Implementation Method 1
semiconductor nanorods with reduced diameters to increase the band gap energy, reducing leakage currents and improving carrier transport properties by shifting from a three-dimensional to a two-dimensional density of states
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2A
AI summary
Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods (403) may be used in the channel region of an access transistor (400). The nanorod diameter can be made small enough to cause an increase in the electronic band gap energy in the channel region of the access transistor, which may serve to limit channel leakage currents in its off -state. In various embodiments, the access transistor may be electrically coupled to a double-sided capacitor (425). Memory devices according to embodiments of the invention, and systems including such devices are also disclosed.