Self-Aligned Planar Electrodes for Nanoscale Channel Devices
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Solution Overview
Problem
One and two dimensional nanoscale materials like graphene and carbon nanotubes face degradation and performance limitations when processed into electronic or photonic devices due to early exposure to semiconductor fabrication steps such as etch processing and annealing, which deteriorate their physical properties.
Innovation Solution
A method is developed to form electrical devices with self-aligned, planar electrodes using 1D or 2D nanoscale materials like carbon nanotubes, graphene, or transition metal dichalcogenides, where these materials are integrated after the gate structure and source/drain contacts are formed, avoiding further processing steps that can degrade their properties, and allowing for scalable device dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 1D or 2D nanoscale materials are processed early in semiconductor fabrication, then device manufacturing progress is achieved, but material degradation and performance limitations occur
Solution Approach 1:
The gate structure and source/drain contacts are formed in advance before the 1D or 2D nanoscale material is integrated. This preliminary formation of the electrode structure allows the nanomaterial to be added later without exposing it to degrading fabrication processes, thus maintaining material reliability while enabling device manufacturing progress
Solution Approach 2:
Instead of the conventional approach of integrating nanomaterials early and then forming electrodes, this patent inverts the sequence by first forming the gate structure and source/drain contacts, then adding the 1D or 2D nanoscale material. This reversal protects the nanomaterial from degradation while achieving the desired device structure
2Ease of manufacture
If conventional processing techniques are used for nanoscale materials, then standard fabrication workflows are maintained, but control and incorporation into semiconductor processing become difficult
Solution Approach 1:
The gate dielectric layer serves as an intermediary that facilitates the integration of 1D or 2D nanoscale materials into standard semiconductor processing. By forming the nanomaterial on the gate dielectric after the gate structure is complete, the patent enables incorporation into conventional workflows while maintaining control over material placement and device performance
3Reliability
If 1D or 2D nanoscale materials are integrated after gate structure formation, then material degradation is minimized, but additional processing steps are required
Solution Approach 1:
The patent merges the nanomaterial integration step with the final device assembly process, combining multiple functions into a unified approach. By integrating the 1D or 2D nanoscale material as the channel region after gate formation, the process achieves material protection while incorporating the nanomaterial function into the existing device structure workflow
Data Source
AI summary
A method of forming an electrical device that includes forming a gate dielectric layer over a gate electrode, forming source and drain electrodes on opposing sides of the gate electrode, wherein one end of the source and drain electrodes provides a coplanar surface with the gate dielectric, and positioning a 1D or 2D nanoscale material on the coplanar surface to provide the channel region of the electrical device.