Nanoscale Etch-Stop Layer for SOI Fabrication
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Solution Overview
Problem
Current methods for fabricating silicon-on-insulator (SOI) substrates, such as SIMOX and BESOI, face challenges like high cost, surface damage, and contamination, as well as the need for time-consuming grinding and chemical etching processes, and require etch-stop layers that suffer from diffusion issues and low selectivity.
Innovation Solution
A high electron mobility transistor (HEMT) is fabricated using a relaxed silicon-germanium layer with a dopant layer containing carbon and/or boron, forming a nanoscale etch-stop layer with a full-width half-maximum (FWHM) thickness of less than 70 nanometers, which reduces diffusion and enhances selectivity, and a strained silicon layer is formed over the relaxed silicon-germanium layer to act as a quantum well device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SIMOX process is used to fabricate SOI substrates, then oxygen implantation creates buried silicon dioxide layer, but the process requires extensive time and is cost prohibitive
Solution Approach 1:
The patent extracts the oxygen implantation step from the SIMOX process and replaces it with thermal oxidation. The buried oxide layer is formed by oxidizing a silicon layer in situ during the fabrication process, eliminating the need for separate oxygen implantation equipment and extensive implantation time.
Solution Approach 2:
The patent changes the process parameters from low-temperature oxygen implantation to high-temperature thermal oxidation. This parameter change transforms the approach from physical implantation to chemical oxidation, significantly reducing process time and equipment requirements while maintaining buried oxide layer quality.
2Reliability
If SIMOX process is used to fabricate SOI substrates, then buried silicon dioxide layer is formed, but high surface damage and contamination occur
Solution Approach 1:
The patent replaces the mechanical/physical oxygen implantation process with a chemical thermal oxidation process. This substitution eliminates the high-energy ion bombardment that causes surface damage and contamination, using instead a controlled chemical reaction to form the buried oxide layer.
3Manufacturing precision
If BESOI process is used to transfer device layer, then grinding and polishing are required to thin the wafer, but these processes are time-consuming
Solution Approach 1:
The patent performs preliminary thinning of the device layer during the bonding process itself. By controlling the bonding conditions and using a sacrificial layer approach, the device layer is transferred at the desired thickness without requiring subsequent extensive grinding and polishing operations.
4Ease of manufacture
If conventional etch-stop layers are used in BESOI, then layer transfer is enabled, but diffusion issues and low selectivity occur
Solution Approach 1:
The patent uses a composite etch-stop layer structure comprising multiple materials with complementary properties. This composite approach provides both the necessary etch selectivity for layer transfer and resistance to diffusion, combining the advantages of different materials to overcome the limitations of single-material etch-stop layers.
Solution Approach 2:
The patent applies different materials with specific properties at different locations within the etch-stop layer. The etch-stop layer has varying composition and thickness to provide high etch selectivity at the interface where it is needed, while maintaining stability and preventing diffusion in other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a robust etch-stop layer with high selectivity and reduced diffusion, enabling more efficient and precise fabrication of SOI substrates with improved electron mobility and device performance.
Implementation Method 1
reduces diffusion and enhances selectivity
Implementation Method 2
a relaxed silicon-germanium layer formed over the substrate
Data Source
AI summary
Various embodiments include forming a silicon-germanium layer over a substrate of a device; forming a layer in the silicon-germanium layer, the layer including at least one of boron and carbon; and forming a silicon layer over the silicon-germanium layer. Additional embodiments are described.