Nanoscale Floating Gate Nanorod for Memory Array Density
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Solution Overview
Problem
The scaling of memory cells in flash memory devices is limited by the need to maintain coupling between the control gate and the floating gate while minimizing interference between adjacent floating gates, leading to increased parasitic coupling and reduced array density.
Innovation Solution
The use of a nanorod structure for the floating gate, which extends from a first portion overlying a tunnel dielectric layer, allows for increased coupling with the control gate while maintaining reduced spacing between adjacent cells, thereby reducing parasitic capacitance and enhancing array density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled down to increase array density, then more cells can be placed in the same area, but parasitic coupling between adjacent floating gates increases
Solution Approach 1:
The floating gate is transformed from a planar structure into a three-dimensional nanorod structure that extends vertically from the tunnel dielectric layer. This dimensional change allows the floating gate to maintain adequate coupling with the control gate while physically separating adjacent floating gates in the lateral direction, thereby reducing parasitic coupling between neighboring cells
Solution Approach 2:
The floating gate is divided into two distinct portions: a first portion that overlies the tunnel dielectric layer and provides coupling to the control gate, and a second portion in the form of a nanorod that extends from the first portion. This segmentation allows each portion to fulfill different functional requirements - coupling and isolation
2Quantity of substance
If spacing between adjacent memory cells is reduced to increase array density, then more cells fit in the same area, but interference between adjacent floating gates increases
Solution Approach 1:
By extending the floating gate vertically into a nanorod structure, the design moves the coupling function into the vertical dimension while lateral spacing can be minimized. This allows adjacent cells to be placed closer together without increasing parasitic coupling, as the nanorod structure confines the electric field primarily in the vertical direction
3Reliability
If control gate coupling to floating gate is increased to improve memory cell performance, then read/write operations are enhanced, but parasitic capacitance increases
Solution Approach 1:
The nanorod structure concentrates the coupling area between the control gate and floating gate in a localized vertical region, while the lateral dimensions are minimized. This creates strong local coupling for improved performance while limiting the overall capacitance to adjacent structures through reduced lateral footprint
Data Source
AI summary
A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.