Front-Side-Cut Backside Source/Drain Contacts for Nanoscale IC Scaling
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Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of integrated circuits to the 10 nanometer node or sub-10 nanometer range, leading to challenges in optimizing device performance and integrating new technologies for future technology nodes, particularly in multi-gate transistors fabricated on bulk silicon substrates.
Innovation Solution
The implementation of front-side-cut backside source or drain contacts, which involve direct power delivery from the backside of the wafer, simplifies the process flow, reduces process complexity, and enables backside contact of source/drain structures, allowing for improved scaling and reduced electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing process infrastructure can be maintained, but manufacturing precision and device performance deteriorate at 10nm node and below
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming sacrificial nanowire structures, creating gate electrodes, removing sacrificial material, and forming source/drain contacts. This segmentation allows each stage to be optimized independently, achieving the required manufacturing precision at 10nm node while managing overall process complexity through modular approach
Solution Approach 2:
Sacrificial nanowire structures are formed in advance before the actual device fabrication. These preliminary structures serve as templates that guide subsequent processing steps, enabling precise positioning of gate electrodes and source/drain contacts without requiring complex alignment processes at the final stage
2Productivity
If transistor size is reduced to increase density, then capacity increases, but variability in fabrication processes worsens and limits scalability
Solution Approach 1:
The sacrificial nanowire structures self-align to form the basis of the transistor architecture. The gate electrode formation and source/drain contact positioning are guided by these self-formed structures, eliminating the need for multiple high-precision alignment steps that would otherwise compound variability as transistor density increases
Solution Approach 2:
The invention changes the physical state and dimensions of sacrificial nanowire structures (diameter, length, material composition) to control the final transistor dimensions. By adjusting these parameters during sacrificial structure formation, the desired transistor size and density are achieved while maintaining uniformity across the wafer
3Ease of manufacture
If front-side contacts are used for source/drain, then process flow is simpler, but electrical resistance increases and performance deteriorates
Solution Approach 1:
Instead of forming source/drain contacts from the front side of the substrate, the invention forms them from the back side. This inversion allows direct access to the source/drain regions without traversing the entire thickness of the substrate through the front side, reducing the contact path length and electrical resistance while maintaining process simplicity
4Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates, then cost is reduced and compatibility with existing infrastructure is improved, but device performance optimization becomes more difficult
Solution Approach 1:
The invention uses composite structures combining sacrificial nanowire materials (such as silicon germanium) with bulk silicon substrates. The sacrificial material provides the necessary structural template for multi-gate formation, while the bulk silicon substrate maintains compatibility with existing fabrication infrastructure. The composite approach enables precise control of device characteristics through material composition tuning
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
Integrated circuit structures having front-side-cut backside source or drain contacts are described. In an example, an integrated circuit structure includes a first gate stack over a first plurality of horizontally stacked nanowires or fin, and a second gate stack over a second plurality of horizontally stacked nanowires or fin. A first epitaxial source or drain structure is at an end of the first plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a backside contact structure thereon. A second epitaxial source or drain structure is at an end of the second plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is laterally between and in contact with the backside dielectric structure and the backside contact structure.