Nanoscale Memory Substrate Bonding via Microscale Interconnects
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Solution Overview
Problem
The challenge in electronic devices is to integrate nanoscale and microscale circuitry effectively, as conventional supporting circuitry for nanoscale memory devices is inefficiently scaled, leading to space constraints and increased complexity, particularly in racetrack memory systems where nanoscale components are densely packed but require microscale supporting infrastructure.
Innovation Solution
The solution involves coupling nanoscale electronic components to microscale components using substrates with bond pads configured in specific patterns, such as honeycomb or raster patterns, and employing conductive bumps to connect these substrates, allowing for efficient integration of nanoscale circuitry with microscale support circuitry, enabling improved coverage and reduced bond pad count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional supporting circuitry is formed on nanoscale memory devices, then storage capacity increases, but manufacturing efficiency and economic viability deteriorate
Solution Approach 1:
The device is divided into two separate substrates: a first substrate containing nanoscale memory cells and a second substrate containing microscale supporting circuitry. This segmentation allows each substrate to be optimized and manufactured independently at its appropriate scale, resolving the contradiction between increased storage capacity and manufacturing efficiency.
Solution Approach 2:
The solution transitions from a single-plane integration approach to a three-dimensional stacked architecture. By vertically stacking the nanoscale memory substrate with the microscale supporting circuitry substrate, the patent enables both high-density storage and efficient manufacturing of supporting functions in separate layers.
2Quantity of substance
If circuitry is made smaller to increase density, then storage capacity increases, but device complexity increases
Solution Approach 1:
By separating the device into two functional substrates, the patent reduces the complexity of each individual substrate. The first substrate focuses solely on high-density memory cells while the second substrate handles supporting functions, avoiding the complexity of integrating all functions at nanoscale on a single chip.
Solution Approach 2:
Bond pads and conductive bumps serve as intermediary elements that facilitate electrical connection between the two substrates. These intermediaries simplify the integration process by providing standardized interfaces between the nanoscale memory array and microscale supporting circuitry, reducing overall device complexity.
3Reliability
If more bond pads are used to connect substrates, then electrical connectivity improves, but real estate is consumed
Solution Approach 1:
The patent transitions from planar bond pad arrangements to a three-dimensional connection architecture using vertical conductive bumps. This dimensional change allows electrical connectivity to be established through the thickness of the substrates rather than requiring extensive lateral spacing, thereby improving connectivity while conserving surface area.
Data Source
AI summary
Electronic devices may include a first substrate including circuitry components within the substrate, a microscale bond pad on a surface of the substrate, and a via electrically connecting the microscale bond pad to one of the circuitry components. A distance between centers of at least some adjacent circuitry components of the circuitry components may be a nanoscale distance. A second substrate may be electrically connected to the microscale bond pad. Methods of forming electronic devices may involve positioning a first substrate adjacent to a second substrate and electrically connecting the second substrate to a microscale bond pad on a surface of the first substrate. The first substrate may include circuitry components within the first substrate and a via electrically connecting the microscale bond pad to one of the circuitry components. A distance between centers of at least some adjacent circuitry components of the circuitry components may be a nanoscale distance.