Nanosecond Laser Annealing for Semiconductor Gate Stack NBTI Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face challenges in achieving high performance and reliability due to the trade-off between gate dielectric thickness and negative-bias temperature instability (NBTI), with existing annealing methods either degrading or failing to improve NBTI reliability.
Innovation Solution
The use of multiple nanosecond pulsed laser anneals at peak temperatures below the melting point of semiconducting materials, applied to a high-k gate stack post-deposition, to improve NBTI reliability without inducing micro-crystallization or re-crystallization, thereby enhancing dopant activation and material properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple nanosecond pulsed laser anneals are applied at peak temperature below melting point, then NBTI reliability is improved, but dopant activation efficiency deteriorates compared to melt annealing
Solution Approach 1:
The patent changes the temperature parameter by maintaining peak anneal temperature below the melting point of the semiconducting material (e.g., below 1414°C for silicon). This submelt temperature regime fundamentally alters the annealing mechanism, preventing melt-induced damage while still achieving dopant activation through thermal diffusion, thereby improving NBTI reliability
Solution Approach 2:
The patent applies multiple periodic nanosecond laser pulses (e.g., 10-100 pulses) to the gate stack. This periodic thermal stimulation accumulates thermal energy over time, enabling sufficient dopant activation through repeated thermal diffusion cycles without requiring any single pulse to reach melting temperature, thus resolving the contradiction between reliability and activation efficiency
2Reliability
If gate dielectric thickness is increased, then reliability is improved, but device performance deteriorates
Solution Approach 1:
The patent changes the temperature parameter of the annealing process (maintaining it below the melting point), which fundamentally alters the physical mechanism from melt-induced damage to thermal diffusion. This enables the use of thicker gate dielectrics without the performance degradation caused by conventional high-temperature or melt annealing, as the submelt process preserves dielectric integrity while still achieving adequate dopant activation
3Productivity
If conventional millisecond-scale laser annealing is used, then dopant activation is efficient, but micro-crystallization or re-crystallization occurs degrading NBTI reliability
Solution Approach 1:
The patent changes the temperature parameter by constraining the peak anneal temperature to remain below the melting point of the semiconducting material. This prevents the phase transition to molten state that causes micro-crystallization and re-crystallization in conventional annealing, while still achieving dopant activation through cumulative thermal diffusion from multiple nanosecond pulses
Solution Approach 2:
The patent uses multiple periodic nanosecond laser pulses to deliver cumulative thermal energy. This periodic thermal stimulation achieves sufficient dopant activation through repeated thermal diffusion cycles without allowing the material to reach melting temperature, thereby avoiding the micro-crystallization damage associated with conventional single high-temperature annealing events
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significant improvement in NBTI reliability, measured by approximately 200 mV of maximum gate voltage using the Voltage-Ramp-Stress method, while maintaining equivalent oxide thickness and mobility, counterintuitively showing effectiveness with submelt nanosecond anneals.
Implementation Method 1
exposing a gate stack formed on a semiconducting material to multiple nanosecond laser pulses at a peak temperature below a melting point of the semiconducting material
Implementation Method 2
At such short anneals, thermal activation of dopants can be inefficient
Data Source
AI summary
Semiconductor structures and methods of fabricating the same using multiple nanosecond pulsed laser anneals are provided. The method includes exposing a gate stack formed on a semiconducting material to multiple nanosecond laser pulses at a peak temperature below a melting point of the semiconducting material.