Nanosheet Source/Drain Air-Gap Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge in semiconductor manufacturing is reducing parasitic capacitance between source/drain features and gate while maintaining desired K value for devices as ICs scale down.
Innovation Solution
A semiconductor device structure is fabricated with a stack of semiconductor layers, including alternating first and second semiconductor layers with different etch selectivity and oxidation rates, forming nanosheet channels surrounded by a gate electrode, and utilizing dielectric layers to reduce parasitic capacitance through selective etching and epitaxial growth of source/drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then productivity increases and costs decrease, but parasitic capacitance between source/drain features and gate increases
Solution Approach 1:
A dielectric layer is introduced as an intermediary material between the source/drain features and the gate electrode. This dielectric layer acts as a mediator that reduces the parasitic capacitance coupling between these components while allowing the device to maintain scaled dimensions for high functional density.
Solution Approach 2:
The patent modifies the electrical parameters of the device by introducing a dielectric material with specific permittivity characteristics between the source/drain and gate. This parameter change reduces the capacitance value without requiring changes to the physical geometry scaling, thereby maintaining productivity benefits while reducing parasitic effects.
2Productivity
If geometry size is decreased to increase functional density, then manufacturing costs decrease, but maintaining desired K value becomes more challenging
Solution Approach 1:
The patent adjusts electrical parameters through material selection rather than relying solely on geometric scaling. By choosing dielectric materials with appropriate permittivity values, the K value (drive current) can be maintained at desired levels even as the device geometry is scaled down to increase functional density.
Solution Approach 2:
The device structure employs composite materials including the dielectric layer combined with semiconductor and conductive materials. This composite approach allows optimization of electrical characteristics such as K value while maintaining the scaled geometry needed for high functional density, thereby simplifying manufacturing precision requirements.
3Area of stationary object
If source/drain features are formed closer to gate to increase functional density, then area utilization improves, but parasitic capacitance increases
Solution Approach 1:
The dielectric layer serves as a mediator that enables source/drain features to be positioned closer to the gate electrode without increasing parasitic capacitance. This intermediary material allows improved area utilization while maintaining electrical isolation that prevents capacitance coupling.
Solution Approach 2:
The patent applies local quality by introducing the dielectric material specifically in the region between the source/drain features and the gate electrode. This localized modification reduces parasitic capacitance only where needed, allowing other areas of the device to maintain high density configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively reduces parasitic capacitance and enhances device performance by minimizing leakage and capacitance between source/drain features and gate, improving efficiency and yield.
Implementation Method 1
reduce parasitic capacitance between source/drain features and gate
Implementation Method 2
minimizing leakage and capacitance between source/drain features and gate
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate and between two adjacent semiconductor layers, an inner spacer disposed between and in contact with one of the semiconductor layers and the substrate, and a dielectric layer structure disposed between the S/D feature and the substrate, the dielectric layer structure comprising a first dielectric layer in contact with the inner spacer and the substrate, and a second dielectric layer nested within the first dielectric layer, wherein a bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer, and a bottom surface of the S/D feature, the first dielectric layer, the second dielectric layer, and the inner spacer define an air gap therebetween.