Nanosheet Air-Gap Source/Drain Isolation for Epitaxy and Capacitance
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Solution Overview
Problem
Current nanosheet devices face challenges in achieving high-quality epitaxially grown source/drain regions while minimizing parasitic capacitance, as conventional full bottom dielectric isolation methods compromise the quality and stress of these regions.
Innovation Solution
An air gap is formed between the epitaxially grown source/drain region and the semiconductor substrate, eliminating the need for dielectric isolation beneath the channel region, thereby allowing for high-quality epitaxial growth and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a full bottom dielectric isolation layer is employed to shut-off substrate leakage and reduce parasitic capacitance, then parasitic capacitance is reduced, but source/drain region quality deteriorates due to epitaxial growth on dielectric material
Solution Approach 1:
The isolation structure is segmented into two parts: a full bottom dielectric isolation layer for substrate leakage shut-off, and a localized air gap structure beneath the source/drain region. This segmentation allows the air gap to provide additional isolation without interfering with epitaxial growth, as the source/drain region grows on the semiconductor substrate surface rather than on the dielectric layer.
Solution Approach 2:
An air gap is introduced as an intermediary structure between the source/drain region and the full bottom dielectric isolation layer. This air gap provides electrical isolation and reduces parasitic capacitance while allowing the source/drain region to be epitaxially grown directly on the semiconductor substrate, thereby maintaining high material quality.
2Loss of energy
If source/drain regions are epitaxially grown on a full bottom dielectric isolation layer, then parasitic capacitance is reduced, but lattice mismatch stress increases
Solution Approach 1:
The air gap structure extracts the isolation function from the full bottom dielectric layer's interface with the source/drain region. By creating a void space between the source/drain region and the dielectric isolation layer, the harmful lattice mismatch stress is eliminated while the dielectric layer continues to provide substrate leakage shut-off.
3Reliability
If a full bottom dielectric isolation layer is used, then substrate leakage is shut-off, but device complexity increases due to additional processing steps
Solution Approach 1:
The air gap formation process is merged with the existing source/drain region fabrication steps. The same epitaxial growth and patterning processes that form the source/drain regions also define the air gap boundaries, eliminating the need for separate air gap formation steps and reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in nanosheet devices with high-quality source/drain regions and reduced parasitic capacitance, enhancing device performance and efficiency.
Implementation Method 1
reduce parasitic capacitance
Implementation Method 2
epitaxially grown from a semiconductor surface
Data Source
AI summary
A nanosheet device is provided that has high quality epitaxially grown source/drain regions and reduced parasitic capacitance which are afforded by forming an air gap between an epitaxially grown source/drain region and a semiconductor substrate. The isolation provided by the air gap does not need to extend beneath the channel region of the nanosheet device.