Nanosheet Airgap Spacer Layout for Lower Gate Fringe Capacitance
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Solution Overview
Problem
In semiconductor device manufacturing, the reduction of parasitic capacitance is challenging, especially in smaller transistor devices where fringing parasitic capacitance between the gate and source/drain can significantly impact transient response, and existing methods using air gaps are ineffective if not properly formed, leading to decreased performance.
Innovation Solution
A nanosheet transistor design with a spacer region including a first and second nanosheet stack and an inner spacer region with an air gap between them, along with a side subway region along the edge, is fabricated by forming sacrificial inner spacers and epitaxial layers, and then removing the sacrificial layers to create an air gap, which reduces parasitic capacitance by using air gaps effectively between the high-k metal gate and the epitaxial layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If air gaps are formed between stacked nanosheets to reduce parasitic capacitance, then transient response is improved, but manufacturing precision is worsened due to difficulty in properly forming the air gaps
Solution Approach 1:
A sacrificial inner spacer material is introduced as an intermediary between the stacked nanosheets. This sacrificial material is deposited conformally and then selectively removed to create the air gap. The intermediary approach solves the manufacturing precision problem by providing a controlled method to form air gaps that would be difficult to create directly, while achieving the desired parasitic capacitance reduction.
Solution Approach 2:
The sacrificial inner spacer is deposited in advance before the air gap is needed. This preliminary action allows the air gap formation to be integrated into the existing manufacturing flow without requiring precise post-processing steps. The sacrificial material is placed beforehand, then removed through selective etching, ensuring the air gap is properly formed without compromising manufacturing precision.
2Area of stationary object
If vertically stacked nanosheets are used to reduce device size, then area efficiency is improved, but parasitic capacitance increases due to closer spacing between gate and source/drain
Solution Approach 1:
The space between stacked nanosheets is segmented into distinct regions: the inner spacer region with air gap for capacitance reduction, and the side subway region maintaining structural integrity. This segmentation allows the air gap to be positioned precisely where it can reduce parasitic capacitance between gate and source/drain, while preserving the compact vertically stacked configuration for area efficiency.
Solution Approach 2:
The air gap is created locally in the inner spacer region between specific nanosheets, rather than uniformly throughout the entire device. This local quality approach reduces parasitic capacitance at the critical interfaces between gate and source/drain areas, while maintaining the overall compact stacked structure for area efficiency. The side subway region retains solid material to preserve structural integrity.
Data Source
AI summary
Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.