Backside Contact Formation in Nanosheet ICs for Leakage Control

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Solution Overview

Problem

Integrated circuit devices with power delivery networks on the backside face challenges in operational reliability due to leakage currents and complex, highly densified structures.

Innovation Solution

A method involving the alternately stacking sacrificial and channel layers, etching to form nanosheet stacks, creating placeholders and source/drain regions, forming gate structures, and etching the substrate to create a backside insulating structure with a liner and contact, enhancing the structural integrity and reliability of the device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a PDN is formed on the backside of a highly-integrated integrated circuit device, then power transmission efficiency is improved, but leakage current increases and operational reliability degrades

Engineering Contradiction:
Improvepower transmission efficiencyVSAvoidoperational reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The device is divided into multiple functional layers including front-side active regions, back-side power delivery networks, and intermediate insulating structures. This segmentation allows power transmission functions to be separated from signal processing functions, enabling efficient power delivery while maintaining operational reliability through spatial isolation of different functional zones

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the device are assigned different structural characteristics: the front surface contains doped semiconductor regions for active device operation, while the back surface contains the PDN structure with conductive layers and insulating structures. This local differentiation optimizes each region for its specific function while minimizing interference between functions

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If the integrated circuit device is highly densified with complex structure, then integration capacity is improved, but leakage current increases and operational reliability degrades

Engineering Contradiction:
Improveintegration capacityVSAvoidoperational reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from planar integration to three-dimensional stacked architecture with front-side active devices and back-side power networks. This vertical dimensionality change enables higher integration capacity by utilizing the third dimension, while maintaining reliability through proper isolation of functional layers

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple functional structures are nested within each other: insulating structures are embedded within the substrate, conductive layers are positioned between insulating layers, and active devices are formed in doped regions. This nested arrangement maximizes space utilization for high integration while maintaining proper electrical isolation

Inventive Principle:
Principle #7Nested doll (Nesting)

3Manufacturing precision

If sacrificial layers are used to form nanosheet stacks, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvenanosheet formation precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Sacrificial layers are deposited and patterned in advance before forming the final nanosheet structure. These preliminary sacrificial structures serve as templates that guide subsequent etching processes, enabling precise nanosheet formation while simplifying the overall manufacturing sequence

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Sacrificial layers act as intermediary structures that facilitate the formation of complex nanosheet stacks. These temporary structures enable precise pattern transfer through self-aligned etching processes, after which they are removed to reveal the final nanosheet architecture

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260040657A1Method of manufacturing integrated circuit device
Publication Date: 2026.02.05 SAMSUNG ELECTRONICS CO LTD
  • US20260040657A1 patent drawing
  • US20260040657A1 patent drawing
  • US20260040657A1 patent drawing

AI summary

A method includes alternately stacking a plurality of sacrificial layers and a plurality of channel layers on a first surface of a substrate; dividing the plurality of channel layers into a plurality of nanosheet stacks; forming a placeholder and a source/drain region on the placeholder between the plurality of nanosheet stacks; forming a first gate structure in an area from which the plurality of sacrificial layers have been removed; etching a portion of a second surface of the substrate to form an opening in the substrate and forming a backside insulating structure in the opening; etching the substrate so that at least a portion of the placeholder is exposed; removing the placeholder; and forming a liner on at least a portion of a side surface of the substrate from which the placeholder has been removed and forming a backside contact on the liner.