Backside Gate Isolation Structure for Lower-Height Nanosheet Cells
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Solution Overview
Problem
Existing cut metal gate (CMG) processes in semiconductor fabrication face challenges in further reducing cell heights and maintaining a reasonable processing window due to the restrictive nature of dielectric fins, which can lead to defects and degraded performance.
Innovation Solution
The formation of gate cut features from the backside of the substrate, independent of dielectric fins, allowing for further scaling down of cell heights and increased processing window, with self-aligned processes to avoid mask misalignment and defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If dielectric fins are used to form gate cut features from the front side, then gate isolation is achieved, but cell height reduction is restricted and processing window deteriorates
Solution Approach 1:
The patent inverts the conventional approach by forming gate cut features from the backside of the substrate rather than the front side. This allows the gate electrode to be segmented after formation without requiring front-side dielectric fins, thereby enabling further cell height reduction while maintaining a reasonable processing window and avoiding the restrictive nature of traditional dielectric fin structures
2Reliability
If dielectric fins are used for gate cut features, then gate isolation is achieved, but defects increase and performance degrades
Solution Approach 1:
By inverting the formation approach to create gate cut features from the backside, the patent eliminates the need for front-side dielectric fins that generate defects and degrade performance. The backside formation method provides a cleaner process that avoids the harmful effects associated with dielectric fin structures
Solution Approach 2:
The patent uses a sacrificial layer that is removed after gate electrode formation, creating a copy of the desired gate cut structure. This sacrificial layer approach allows for precise gate isolation without the defects inherent in permanent dielectric fin structures
3Ease of manufacture
If photolithography and etch processes are used from the front side, then gate cut features are formed, but mask misalignment occurs and complexity increases
Solution Approach 1:
The patent performs photolithography and etching from the backside of the substrate, which simplifies the process by eliminating the need for precise front-side mask alignment. The backside approach allows for self-aligned formation of gate cut features that naturally align with the gate electrode without requiring high-precision overlay
Solution Approach 2:
The backside formation process is self-aligned, where the gate cut features automatically align with the gate electrode structure without requiring additional alignment steps or complex mask patterns, thereby reducing manufacturing complexity and improving precision
Data Source
AI summary
A semiconductor device includes nanostructures vertically arranged and spaced apart from one another along a first direction. The semiconductor device also includes a dielectric fin structure of a dielectric material of uniform composition and an isolation structure on opposite sides of the nanostructures. Moreover, the semiconductor device also includes a gate structure wrapping around the nanostructures. The gate structure extends between the nanostructure and the dielectric fin structure, and extends between the nanostructures and the isolation structure. Furthermore, the nanostructures are spaced apart from the dielectric fin structure along a second direction perpendicular to the first direction by a first distance, and from the isolation structure along the second direction by a second distance, where the first distance is greater than the second distance. Additionally, the gate structure interfaces with the dielectric fin structure on a surface extending perpendicular to the first direction.