Backside Power Rail Contacts for Low-Resistance Nanosheet Transistors
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Solution Overview
Problem
Conventional semiconductor fabrication methods face challenges in forming power rails and vias on the backside of integrated circuits (ICs) with reduced resistance and coupling capacitance, leading to increased voltage drop and power consumption as ICs scale down.
Innovation Solution
The method involves forming sacrificial contact vias on the backside of the wafer before channel structures, which are later replaced by conductive contact vias, allowing for wider backside power rails that reduce contact resistance and improve device performance, along with improved overlay control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If power rails are formed above the transistors in conventional stacked-up fashion, then the fabrication process is simpler, but the voltage drop across power rails increases and power consumption increases
Solution Approach 1:
The patent moves power rails from the traditional planar position above transistors to the backside of the substrate, utilizing the third dimension (vertical stacking) to separate power distribution from logic circuits. This dimensional repositioning reduces current path length and resistance while maintaining fabrication feasibility through backside processing techniques.
Solution Approach 2:
Instead of forming power rails in the conventional top-down approach, the patent inverts the process by first forming sacrificial contact vias on the backside of the substrate, then using these as templates to create low-resistance power connections. This inverted approach prioritizes power distribution integrity before logic circuit formation.
2Productivity
If IC geometry size is scaled down to increase functional density, then production efficiency increases and costs decrease, but voltage drop across power rails increases and power consumption increases
Solution Approach 1:
By transitioning to 3D stacked architecture with backside power rails, the patent enables continued scaling of planar dimensions while maintaining efficient power distribution. The vertical separation of power and logic layers allows smaller feature sizes without proportionally increasing power rail resistance.
Solution Approach 2:
The patent changes the physical state and positioning parameters of power rails by moving them to the backside substrate surface, altering the electrical path length and cross-sectional area parameters. This parameter transformation reduces resistance independently of the scaling-down trend in logic circuit dimensions.
3Ease of manufacture
If backside power rails are formed with traditional methods, then the process is straightforward, but contact resistance is high and device performance is limited
Solution Approach 1:
The patent performs preliminary actions by first forming sacrificial contact vias on the backside substrate before main power rail formation. These preliminary structures serve as precise templates and connection points, ensuring optimal positioning and low-resistance contacts are established before subsequent power distribution layer deposition.
Solution Approach 2:
The sacrificial contact vias act as intermediary structures that facilitate the formation of high-quality power connections. These temporary structures enable precise alignment and low-resistance contacts, which are then integrated into the final power rail architecture, improving overall connection reliability.
Data Source
AI summary
A semiconductor structure includes nanostructures vertically stacked, a gate structure wrapping around at least one of the nanostructures, a gate spacer extending along a sidewall of the gate structure, first and second epitaxial features abutting and sandwiching the nanostructures, and a backside metal contact interfacing with a bottom surface of the first epitaxial feature but spaced apart from a bottom surface of the second epitaxial feature. In a cross-sectional view of the semiconductor structure along a lengthwise direction of the nanostructures, the bottom surface of the first epitaxial feature is above the bottom surface of the second epitaxial feature.