Nanosheet Bipolar Junction Transistor Integration with CMOS
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Solution Overview
Problem
Current semiconductor technologies face challenges in integrating nanosheet devices with bipolar junction transistors (BJTs) for scaling beyond 7 nm, as existing methods do not effectively incorporate BJT devices into nanosheet architectures, limiting the scalability and performance of CMOS technology.
Innovation Solution
A method is developed to form both field-effect transistors (FETs) and BJTs on a common substrate using nanosheet stacks, where dummy gates and sacrificial gate materials are used to create source/drain and emitter/collector regions, with doped semiconductor material and metal gate stacks deposited to enhance device performance, allowing for precise control of nanosheet dimensions and increased gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy gates and sacrificial gate materials are used to form source/drain and emitter/collector regions, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Dummy gates are formed preliminarily on the nanosheet stacks before the actual transistor formation. These dummy gates serve as placeholders that define the precise locations where source/drain regions (for FETs) and emitter/collector regions (for BJTs) will be formed. This preliminary action enables precise region formation while the complexity is managed through systematic process design.
Solution Approach 2:
Sacrificial gate materials are used as intermediary structures during fabrication. These materials are deposited between the gate spacers, serve as temporary structures for defining active regions, and are subsequently removed after serving their purpose. This intermediary approach enables precise region formation without permanently increasing device complexity.
2Reliability
If doped semiconductor material is deposited on and around the second nanosheet of the BJT region, then BJT gain is increased, but manufacturing complexity increases
Solution Approach 1:
Doped semiconductor material is deposited selectively on and around the second nanosheet specifically in the BJT region, not throughout the entire device. This local doping approach increases BJT gain by creating the necessary emitter and collector regions with appropriate doping profiles, while limiting the complexity impact to only the BJT fabrication area.
Solution Approach 2:
The doping process extends into the vertical dimension by depositing material on and around the suspended second nanosheet. This three-dimensional doping approach enables comprehensive coverage of the BJT regions (emitter, base, collector) and achieves high BJT gain through precise dopant placement in multiple spatial dimensions.
Data Source
AI summary
A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate. The gate includes a nanosheet extending through a channel region of the gate. The FET includes a pair of source/drains arranged on opposing sides of the gate. The semiconductor device further includes a bipolar junction transistor (BJT) arranged adjacent to the FET on the substrate. The BJT includes an emitter and a collector. The BJT includes a nanosheet including a semiconductor material extending from the emitter to the collector, with a doped semiconductor material arranged above and below the nanosheet.