Nanosheet Transistor Bottom Insulation for Leakage Suppression
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Solution Overview
Problem
As integrated circuit devices shrink in size, they face challenges with unintended leakage current in nanosheet field-effect transistors, leading to deteriorated electrical characteristics, necessitating a novel structure to suppress leakage current and enhance performance.
Innovation Solution
A method of manufacturing integrated circuit devices involves forming a stack structure with alternately stacked sacrificial semiconductor layers and nanosheet semiconductor layers, using local liners to expose specific layers, and replacing sacrificial layers with insulating structures to create a bottom insulating space, thereby improving electrical characteristics by reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of integrated circuit devices is decreased to increase integration density, then the degrees of integration increase, but unintended leakage current increases and electrical characteristics deteriorate
Solution Approach 1:
The active region is segmented into multiple nanosheets stacked vertically, creating multiple independent conduction channels. This segmentation allows each nanosheet to be controlled independently by the gate, improving overall device performance while maintaining compact footprint. The segmentation also introduces insulating spaces between nanosheets to suppress leakage current.
Solution Approach 2:
The invention transitions from a planar two-dimensional transistor structure to a three-dimensional vertical stack structure. Multiple nanosheets are stacked in the vertical dimension, allowing increased integration density without proportionally increasing the lateral footprint. This dimensional change enables better gate control and leakage suppression through vertical insulation.
2Productivity
If horizontal nanosheets are stacked on the same layout regions to increase integration, then the degrees of integration increase, but leakage current increases due to unintended conduction paths
Solution Approach 1:
Insulating spaces are extracted and introduced between adjacent nanosheets in the vertical stack. These insulating spaces remove the harmful leakage current paths that would otherwise exist between closely spaced nanosheets, while preserving the beneficial vertical stacking for increased integration.
Solution Approach 2:
Insulating materials are introduced as intermediary layers between adjacent nanosheets. These intermediary insulating spaces act as barriers that block unintended charge carrier transport between nanosheets, suppressing leakage current while allowing the nanosheets to remain in close proximity for compact device design.
Data Source
AI summary
A method of manufacturing an integrated circuit device includes forming, on a substrate, a fin-type active region and a stack structure in which sacrificial semiconductor layers and nanosheet semiconductor layers are alternately stacked one-by-one, forming a first local liner on a sidewall of the stack structure to cover a sidewall of a bottom sacrificial semiconductor layer, which is closest to the fin-type active region and expose sidewalls of other sacrificial semiconductor layers, forming a second local liner on the sidewall of the stack structure to cover the sidewalls of the other sacrificial semiconductor layers except for the bottom sacrificial semiconductor layer, exposing the bottom sacrificial semiconductor layer by removing the first local liner, forming a bottom insulating space exposing a fin top surface of the fin-type active region by removing the bottom sacrificial semiconductor layer, and forming a bottom insulating structure in the bottom insulating space.