Nanosheet Transistor Bottom Isolation for Leakage Suppression
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Solution Overview
Problem
The existing bottom isolation layer in nanosheet field effect transistors (FETs) is damaged by subsequent process steps, leading to increased parasitic source-to-drain leakage and degradation in device performance, particularly as transistor gate length scales to 12 nm.
Innovation Solution
An enhanced bottom dielectric isolation is achieved by forming alternating layers of sacrificial and semiconductor channel materials into nanosheet stacks, with a sacrificial gate and subsequent removal of the stack sacrificial layer to create a cavity, followed by deposition of a first and second layer that protects the bottom isolation layer from further damage during aggressive processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bottom isolation layer is used, then the device structure is simple, but the isolation layer becomes damaged by subsequent process steps, increasing parasitic source-to-drain leakage
Solution Approach 1:
The patent forms the bottom isolation layer before subsequent aggressive process steps (etching, cleaning) are performed on the device structure. This preliminary formation allows the isolation layer to be in place to prevent epitaxial growth from the substrate during these later processes, rather than attempting to protect it during damage and then repair it.
Solution Approach 2:
The isolation structure is segmented into multiple functional layers: a bottom isolation layer formed in a trench, and additional isolation layers formed later in the cavity. This segmentation allows each layer to serve specific purposes - the bottom layer prevents substrate epitaxial growth while upper layers provide additional isolation and structural support.
2Reliability
If the bottom isolation layer is formed early, then it can prevent epitaxial growth from the substrate, but it becomes damaged by subsequent etching and cleaning processes
Solution Approach 1:
The bottom isolation layer is formed preliminarily before the aggressive etching and cleaning steps. This timing allows it to be in place to prevent epitaxial growth from the substrate during these processes, addressing the reliability requirement before the damage occurs.
Solution Approach 2:
The patent creates a protective structure by forming the isolation layer in a trench with specific geometry and material composition that cushions it against subsequent process damage. The trench structure and layer configuration provide a buffer that reduces the impact of aggressive etching and cleaning steps on the isolation layer's effectiveness.
3Ease of manufacture
If process steps are performed after bottom isolation layer formation, then device fabrication can proceed, but the isolation layer effectiveness is reduced
Solution Approach 1:
The bottom isolation layer is formed as a preliminary step in the fabrication sequence, establishing the isolation function before subsequent device formation steps. This allows normal fabrication processes to proceed while the isolation layer is already in place to prevent epitaxial growth.
Solution Approach 2:
The isolation function is segmented into multiple layers formed at different times: the bottom isolation layer formed early to prevent substrate epitaxial growth, and additional isolation layers formed later to provide enhanced protection and isolation. This segmentation allows each layer to address specific reliability concerns while maintaining fabrication processability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced bottom dielectric isolation effectively reduces source-drain leakage by preventing epitaxial growth from the substrate and protecting the isolation layer from subsequent etching and cleaning processes, thereby maintaining device performance.
Implementation Method 1
forming a stack of nanosheet layers on the stack sacrificial layer
Implementation Method 2
forming a stack of nanosheet layers on the stack sacrificial layer
Implementation Method 3
forming a cavity by removing the stack sacrificial layer
Implementation Method 4
deposition of a first and second layer that protects the bottom isolation layer
Implementation Method 5
deposition of a first and second layer that protects the bottom isolation layer
Data Source
AI summary
A semiconductor nanosheet device including semiconductor channel layers vertically aligned and stacked one on top of another, separated by a work function metal, and a second layer between two first layers, the second layer and two first layers between the semiconductor channel layers and a substrate. A semiconductor device including a lower first layer, a second layer, and a source drain region between a first set of semiconductor channel layers vertically aligned and stacked one on top of another, and a second set of semiconductor channel layers. A method including forming a stack sacrificial layer, a stack of nanosheet layers, forming a cavity by removing the stack sacrificial layer, and simultaneously forming a first layer on an upper surface of the stack sacrificial layer, on vertical side surfaces of the set of sacrificial gates, and an upper first layer and a lower first layer in a portion of the cavity.