Nanosheet Transistor Buffer Layer for Parasitic Capacitance Reduction
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Solution Overview
Problem
Nanosheet FETs face challenges in reducing parasitic capacitance and leakage currents due to under channel pathways, which degrade device performance, and conventional methods to suppress these pathways have not been fully successful.
Innovation Solution
A buffer layer with lower conductivity than the channel nanosheets is formed between the substrate and the nanosheets, and an oxide layer is deposited to create an isolation dielectric layer between the gate and the substrate, reducing capacitive coupling and preventing under channel pathways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate wraps around the full perimeter of multiple nanosheet channels in a gate-all-around configuration, then fuller depletion in the channel regions is achieved and short-channel effects are reduced, but parasitic capacitance and leakage currents increase due to under channel pathways
Solution Approach 1:
A buffer layer is introduced as an intermediary between the substrate and the nanosheet channels. This buffer layer has lower conductivity than the channel nanosheets, serving as a mediator that blocks leakage currents while maintaining the beneficial gate-all-around configuration for short-channel effects control
Solution Approach 2:
The buffer layer is selectively positioned only in specific regions where under channel pathways exist, creating local quality changes. The buffer layer has different conductivity properties compared to the channel nanosheets, allowing it to specifically target and block leakage paths without affecting the overall channel performance
2Object-generated harmful factors
If conventional methods are used to suppress under channel pathways, then some leakage reduction is achieved, but the methods are not fully successful in eliminating parasitic capacitance and leakage currents
Solution Approach 1:
The conductivity parameter of the buffer layer is specifically engineered to be lower than that of the channel nanosheets. This parameter change creates an electrical property gradient that directs current flow through the desired channel path while blocking alternative leakage paths, achieving superior leakage suppression compared to conventional methods
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces parasitic capacitance and leakage currents by increasing the dielectric thickness between the gate and substrate, ensuring current flows through the channel nanosheets rather than the buffer layer, thereby enhancing device performance.
Implementation Method 1
The buffer layer has a lower conductivity than the channel nanosheet
Implementation Method 2
depositing an oxide layer on the buffer layer... creating an isolation dielectric layer between the gate and the substrate, reducing capacitive coupling
Data Source
AI summary
Provided is a nanosheet semiconductor device. In embodiments of the invention, the nanosheet semiconductor device includes a channel nanosheet formed over a substrate. The nanosheet semiconductor device includes a buffer layer formed between the substrate and the channel nanosheet. The buffer layer has a lower conductivity than the channel nanosheet.