Nanosheet Transistor Cap Layer for Inner Spacer Protection

Solution Overview

Problem

The existing inner spacers in semiconductor devices, particularly in nanostructure channel FETs, are not entirely satisfactory as they can be damaged during the gate replacement process, leading to reliability issues such as time-dependent dielectric breakdown and Ge diffusion.

Innovation Solution

A silicon-based cap layer is formed on the exposed surfaces of the first and second semiconductor layers before the formation of inner spacers. This cap layer acts as an etch stop and protects the inner spacers from damage during the removal of the second semiconductor layers, thereby enhancing the integrity of the source/drain features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If inner spacers are formed between metal gate and source/drain structure to protect S/D structure during gate replacement process, then the S/D structure is protected from damage, but the inner spacers themselves are damaged during the gate replacement process leading to reliability issues

Engineering Contradiction:

Improvereliability of source/drain structureVSAvoidintegrity of inner spacer

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

A cap layer is formed on the inner spacer before the gate replacement process begins. This preliminary protective layer prevents direct contact between the etching chemicals and the inner spacer during subsequent processing steps, thereby preserving the inner spacer's integrity while still allowing it to fulfill its protective function for the source/drain structure.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The cap layer acts as an intermediary between the inner spacer and the harmful etching environment during gate replacement. This intermediate layer absorbs the protective role during the critical gate removal process, allowing the inner spacer to maintain its structural integrity without being directly exposed to damaging chemicals.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If inner spacers are used to protect source/drain structure, then damage during gate replacement is reduced, but Ge diffusion and time-dependent dielectric breakdown still occur

Engineering Contradiction:

Improveintegrity of source/drain featureVSAvoidGe diffusion and dielectric breakdown

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The cap layer is applied in advance to counteract the harmful effects of Ge diffusion and dielectric breakdown. By establishing this protective barrier before the gate replacement process, the cap layer prevents Ge atoms from migrating and stops dielectric breakdown pathways from forming, thereby eliminating these harmful effects proactively.

Inventive Principle:

Principle #9Preliminary anti-action

Solution Approach 2:

The cap layer, which might seem like an additional complex step, actually simplifies the overall process by converting potential harmful effects (Ge diffusion and dielectric breakdown) into manageable conditions. The cap layer's presence transforms a potentially damaging process environment into a controlled one where these harmful effects are inherently prevented.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The cap layer effectively prevents wire release-induced damages to the source/drain features, reduces Ge diffusion, and minimizes the risk of time-dependent dielectric breakdown, thereby improving the reliability and performance of the semiconductor device.

Implementation Method 1

A silicon-based cap layer is formed on the exposed surfaces of the first and second semiconductor layers before the formation of inner spacers. This cap layer acts as an etch stop and protects the inner spacers from damage during the removal of the second semiconductor layers

Methodology Applied

Scientific EffectEtch stop:

Implementation Method 2

A silicon-based cap layer is formed on the exposed surfaces of the first and second semiconductor layers before the formation of inner spacers. This cap layer acts as an etch stop and protects the inner spacers from damage during the removal of the second semiconductor layers, thereby enhancing the integrity of the source/drain features

Methodology Applied

Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS20250081549A1Semiconductor device having nanosheet transistor and methods of fabrication thereof

Publication Date: 2025.03.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a plurality of semiconductor layers vertically stacked, a plurality of inner spacers, each being disposed between two adjacent semiconductor layers. The structure also includes a source/drain feature in contact with each of the inner spacers, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and a cap layer disposed between the source/drain feature and each of the plurality of the semiconductor layers.