Nanosheet Capacitor Integration in FET Fabrication
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Solution Overview
Problem
Current semiconductor device fabrication processes face challenges in integrating capacitive devices effectively into nanosheet-based field effect transistor (FET) flows, particularly in forming capacitive devices with nanosheet fins that require precise etching and electrode formation to achieve desired external capacitance.
Innovation Solution
A method involving the formation of nanosheet stacks on a substrate, patterning to create fins, ion implantation, annealing, and subsequent deposition of insulator and conductive layers to create electrodes with voids and conductive contacts, allowing for the integration of capacitive devices within existing FET fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional planar capacitor fabrication processes are used, then manufacturing simplicity is maintained, but integration with nanosheet-based FET flows and optimization of external capacitance are compromised
Solution Approach 1:
The patent merges capacitor fabrication with nanosheet-based FET manufacturing by using the same nanosheet stack structure for both devices. The capacitor shares the nanosheet formation, etching, and electrode deposition processes with adjacent FETs, allowing simultaneous fabrication of both device types from a common nanosheet stack without requiring separate processing lines
Solution Approach 2:
The nanosheet stack structure serves multiple functions: it forms the channel region for FETs and simultaneously provides the electrode structure for capacitors. The same alternating semiconductor-dielectric nanosheets that create transistor channels also serve as capacitor electrodes and dielectric layers, enabling a single structure to fulfill multiple device requirements
2Manufacturing precision
If precise etching is performed to form suspended nanosheet fins for capacitors, then external capacitance optimization is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The nanosheet stack is segmented into distinct regions through selective etching: some nanosheets form suspended fins for capacitors while others remain supported for FET channels. This segmentation allows different portions of the same stack to be processed differently, enabling precise control over capacitor geometry and capacitance values while maintaining compatibility with standard FET fabrication
Solution Approach 2:
A sacrificial layer is introduced as an intermediary element during fabrication. This sacrificial material is deposited between the nanosheet stack and the substrate, then selectively removed to create the suspended capacitor structure. The sacrificial layer mediates the formation of complex three-dimensional capacitor geometries from planar nanosheet stacks, simplifying the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the efficient formation of capacitive devices with optimized external capacitance by leveraging existing nanosheet-based FET fabrication processes, enhancing the integration of capacitive components into semiconductor device manufacturing.
Implementation Method 1
ions are implanted in the first fin and the second fin and annealing to form a first electrode and a second electrode
Implementation Method 2
ions are implanted in the first fin and the second fin and annealing to form a first electrode and a second electrode
Data Source
AI summary
A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact is arranged on a basal end of the second electrode.