Nanosheet Cell-Height Scaling With Sacrificial Gate Boundary Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in fabricating semiconductor devices with mixed threshold voltages (Vts) is the difficulty in achieving boundary isolation of multiple patterning gates, particularly in advanced technologies like FinFET devices with nanowires or nanosheets at nodes below 3 nm, where wet over-etching can lead to metal gate material loss and variability in patterning boundaries.
Innovation Solution
An etching back process using a sacrificial layer is employed to remove the n-type work function layer from neighboring p-type device regions without losing metal gate material, ensuring high Vt control and uniformity in both n-type and p-type regions, and minimizing lateral material loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet over-etching is used to remove work function layers, then complete removal can be achieved, but metal gate material loss occurs and patterning boundary variability increases
Solution Approach 1:
A sacrificial layer is introduced as an intermediary material between the work function layer and the metal gate. This sacrificial layer is selectively removed through etch-back processes, allowing the metal gate material to be preserved while still achieving complete work function layer removal. The sacrificial layer acts as a protective mediator that prevents direct contact between the etchant and the metal gate, thereby preventing material loss and maintaining patterning boundary uniformity.
Solution Approach 2:
The metal gate material is deposited in advance before the work function layer removal process. This preliminary deposition ensures that the metal gate structure is already in place and can be protected during subsequent etching operations. The pre-formed metal gate serves as a stable reference structure that prevents variability in patterning boundaries while allowing complete removal of the work function layer through controlled etch-back of the sacrificial layer.
2Productivity
If cell height is reduced for scaling, then device density increases, but control over threshold voltage becomes more difficult
Solution Approach 1:
The gate structure is segmented into distinct functional layers: a metal gate layer for primary control and a work function layer for threshold voltage adjustment. This segmentation allows independent optimization of each layer's thickness and composition, enabling precise threshold voltage control even in scaled devices with reduced cell height. The work function layer can be selectively removed or adjusted without affecting the metal gate structure, providing fine-tuned control over device characteristics.
Solution Approach 2:
The threshold voltage is controlled by changing the parameters of the work function layer, specifically its thickness and material composition. By adjusting these parameters, the threshold voltage can be precisely tuned to desired values. The etch-back process allows dynamic adjustment of the work function layer thickness, providing a mechanism to optimize threshold voltage control as device dimensions are scaled down and cell height is reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for effective boundary isolation of multiple patterning gates, achieving high Vt levels and improved Vt control in semiconductor devices, while conserving cell height and preventing metal gate retreat along the N/P boundary.
Implementation Method 1
An etching back process using a sacrificial layer is employed to remove the n-type work function layer from neighboring p-type device regions
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.