Nanosheet Standard Cell Layout With Equal Cell Heights
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Solution Overview
Problem
The complexity of nanosheet field-effect transistors (FETs) in semiconductor devices poses challenges in design and manufacturing, particularly in achieving equal cell heights with different nanosheet sizes and spacings, which complicates the layout revision process and affects circuit efficiency, area, and power balance.
Innovation Solution
A method for generating standard cells with equal cell heights by selecting nanosheet widths and spacings from a finite set, using specific formulas and tables to ensure compliance with design rules, thereby simplifying the layout revision stage and improving design cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different nanosheet sizes and spacings are used in standard cells, then device performance and circuit efficiency can be optimized, but cell heights become unequal complicating the layout revision process
Solution Approach 1:
The patent applies parameter changes by systematically varying nanosheet widths and spacings from a finite set of predetermined values. By changing these geometric parameters while maintaining equal cell heights through coordinated adjustment, the method achieves diverse device performances without complicating the layout structure, thus resolving the contradiction between adaptability and device complexity
Solution Approach 2:
The patent creates a universal standard cell structure that can accommodate different nanosheet configurations (various widths and spacings) while maintaining a consistent cell height. This multi-functional cell design allows the same basic structure to serve multiple performance requirements, reducing layout revision complexity while preserving adaptability
2Device complexity
If equal cell heights are enforced across different standard cells, then layout revision complexity is reduced, but flexibility in optimizing area, power, and performance balance is limited
Solution Approach 1:
The patent resolves this contradiction by changing multiple parameters simultaneously - specifically, when cell heights are constrained to be equal, the method compensates by varying nanosheet widths and spacings within the finite set. This allows area, power, and performance optimization through parameter adjustment while maintaining the simplifying equal-height constraint
3Ease of manufacture
If nanosheet widths and spacings are selected from a finite set, then design rule compliance is ensured and manufacturing is simplified, but design flexibility is reduced
Solution Approach 1:
The patent addresses this contradiction by defining a finite set of predetermined nanosheet widths and spacings that satisfy manufacturing requirements. Within this constrained parameter space, the method achieves design flexibility through systematic combination and selection of these discrete values, balancing manufacturability with design adaptability
Solution Approach 2:
The patent uses a finite set of standardized nanosheet dimensions that can be repeatedly copied and combined in different configurations. This standardization ensures manufacturing simplicity while the combinatorial use of these copied elements provides sufficient design flexibility for various circuit requirements
Data Source
AI summary
A method includes receiving a design rule deck including a predetermined set of widths and spacings associated with active regions. The method also includes providing a cell library including cells having respective active regions, wherein widths and spacings of the active regions are selected from the predetermined set of the design rule deck. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and a first active region having a first width in the first direction. The second cell has the cell height, and a second active region having a second width in the first direction. The second width is different from the first width. The method further includes manufacturing a semiconductor device according to the design layout.