Nanosheet Standard Cell Layout With Backside Power Isolation
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Solution Overview
Problem
The integration of nanosheet FETs between adjacent standard cells in semiconductor integrated circuits poses challenges due to potential interference with circuit operation, especially with the introduction of interconnects under transistors, leading to increased power consumption and manufacturing discontinuities.
Innovation Solution
A layout structure is implemented where nanosheet FETs are formed between adjacent standard cells with overlapping power lines on the backside of transistors, connected via vias, and orthogonal gate interconnects to ensure continuous active regions and off transistors without influencing circuit operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If nanosheet FETs are formed between adjacent standard cells to improve integration degree, then manufacturing precision and yield are improved, but circuit operation may be influenced negatively
Solution Approach 1:
The patent extracts the problematic boundary region between standard cells and treats it separately by forming dummy transistors that are electrically isolated from the main circuit. This allows the continuous formation of nanosheet FETs across cell boundaries while preventing circuit interference through electrical extraction of the boundary transistors from the functional circuit.
Solution Approach 2:
The patent introduces dummy transistors as intermediary elements at the boundaries between standard cells. These dummy transistors serve as mediators that maintain the continuous nanosheet structure while being electrically isolated through separate power supply connections, thus preventing them from influencing the main circuit operation.
2Productivity
If interconnects are provided on the back of substrate under transistors to achieve higher integration, then integration degree is improved, but power consumption increases significantly
Solution Approach 1:
The patent converts the potentially harmful effect of continuous nanosheet formation (which would create unwanted conducting paths and increase power consumption) into a benefit by using the same continuous formation process to create both functional transistors and isolated dummy transistors. The dummy transistors, though structurally similar, are electrically isolated and thus do not consume power, while still maintaining manufacturing simplicity.
3Manufacturing precision
If standard cells are placed adjacently with continuous active regions to form nanosheet FETs without discontinuities, then manufacturing variations are reduced, but it becomes difficult to prevent interference from boundary transistors
Solution Approach 1:
The patent segments the power supply connections for transistors at standard cell boundaries from the main circuit power supply. By providing separate power supply lines and connections for boundary transistors, the patent maintains continuous active regions for manufacturing simplicity while enabling independent electrical control and isolation of boundary transistors from the main circuit.
Data Source
AI summary
In a semiconductor integrated circuit device, a standard cell includes: an active region forming the channel, source, and drain of a transistor; and a power line formed on the back side of the transistor. A first region in the active region is connected to the power line through a via. A nanosheet contiguous with the active region is formed on a cell boundary. A gate interconnect, which is orthogonal to the nanosheet in planar view, is electrically connected to the first region.