N- and M-Stack Nanosheet Cells for Density-Power Balance
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate due to high integration, necessitating improved methods for forming devices with excellent performance.
Innovation Solution
The semiconductor device includes a substrate with N-stack and M-stack cell regions separated by a buffer cell region, featuring stacked nanosheets in channel patterns and gate electrodes, along with specific manufacturing processes to form gate electrodes and epitaxial patterns, enhancing electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFETs are scaled down to increase integration, then device density is improved, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional stacked nanosheet structures. Multiple nanosheets are stacked vertically to form the channel region, enabling increased device density without further lateral scaling. This vertical stacking approach maintains operating characteristics by providing multiple parallel conduction paths while occupying less footprint area.
Solution Approach 2:
The channel region is segmented into multiple separate nanosheets stacked vertically. Each nanosheet acts as an independent conduction path, and collectively they provide the desired current capability. This segmentation allows the device to achieve high density through vertical stacking rather than lateral scaling, preserving operating characteristics.
2Productivity
If high integration is implemented, then device density is improved, but power consumption increases
Solution Approach 1:
The patent introduces different stack configurations (N-stack and M-stack cells with different numbers of nanosheets) in different regions of the device. This allows local optimization where areas requiring high performance can use deeper stacks while areas requiring lower power consumption use shallower stacks, achieving a balance between density and power efficiency.
Solution Approach 2:
The patent enables dynamic control of power consumption by allowing different regions of the circuit to operate with different nanosheet stack depths. The buffer cell region with intermediate stack depth can be activated only when needed, providing dynamic power adjustment while maintaining high density capability.
3Reliability
If different stack depths are used in adjacent cells, then performance optimization is improved, but manufacturing complexity increases
Solution Approach 1:
The patent introduces a buffer cell region with intermediate stack depth between N-stack and M-stack cells. This buffer region acts as a transition zone that facilitates the manufacturing process by providing a gradual intermediate structure, making it easier to form the different stack depths without requiring abrupt transitions that would complicate the fabrication process.
Solution Approach 2:
The patent forms the buffer cell region with an intermediate number of nanosheets before finalizing the N-stack and M-stack regions. This preliminary formation of the intermediate structure simplifies subsequent processing steps, as the buffer region can serve as a reference or transition zone during the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves electrical performance by allowing high-speed operation in M-stack cells while reducing power consumption in N-stack cells, thus optimizing device functionality.
Implementation Method 1
an N-stack epitaxial pattern between the N-stack channel pattern and the dummy channel pattern; and an M-stack epitaxial pattern between the M-stack channel pattern and the dummy channel pattern
Data Source
AI summary
A semiconductor device includes a substrate including an N-stack cell, a buffer cell and an M-stack cell that are on the substrate, the buffer cell being between the N-stack and M-stack cells, an active pattern extending from the N-stack cell to the M-stack cell via the buffer cell, an N-stack channel pattern on the active pattern of the N-stack cell, an M-stack channel pattern on the active pattern of the M-stack cell, a dummy channel pattern on the active pattern of the buffer cell, an N-stack epitaxial pattern between the N-stack channel pattern and the dummy channel pattern, and an M-stack epitaxial pattern between the M-stack channel pattern and the dummy channel pattern. The N-stack channel pattern includes stacked N semiconductor patterns. The M-stack channel pattern includes stacked M semiconductor patterns. Each of N and M is an integer number of 2 or more, and M is greater than N.