Isolation Elements in Nanosheet CFETs for Parasitic Leakage Prevention
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Solution Overview
Problem
In integrated circuit devices, particularly in 3D monolithic complementary field effect transistors (CFETs), there is a challenge in achieving effective electrical isolation between n-type and p-type epitaxial source/drain regions to prevent parasitic leakage through the substrate, which affects device performance.
Innovation Solution
The implementation of isolation elements such as isolation plugs or buried oxide layers that extend into the substrate, along with liner dielectrics and specific processing methods like selective oxidation, to create self-aligned epitaxial spacers and provide electrical insulation between the source/drain regions of nFET and pFET transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar or fin-type transistor structures are used, then manufacturing and integration are relatively simple, but electrical isolation between n-type and p-type source/drain regions is insufficient leading to parasitic leakage
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to vertically stacked 3D CFET structures. The n-type and p-type transistors are stacked vertically with shared gates, creating three-dimensional integration. This dimensional change enables effective electrical isolation between opposite-polarity source/drain regions through the vertical stacking architecture, preventing parasitic leakage while improving device performance
Solution Approach 2:
The patent divides the transistor structure into distinct stacked segments: n-type transistor layer, p-type transistor layer, and shared gate structures. Each segment is separately formed through selective epitaxial growth and patterning processes. This segmentation allows independent optimization of each transistor type while maintaining electrical isolation between them, resolving the contradiction between isolation effectiveness and structural complexity
2Reliability
If isolation elements extend into the substrate to prevent parasitic leakage, then electrical insulation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms isolation elements (such as oxide layers or doped regions) in the substrate before forming the epitaxial semiconductor layers. This preliminary action establishes the isolation structure in advance, ensuring proper positioning and electrical insulation before the complex stacked transistor structure is built. By preparing isolation elements first, the patent reduces manufacturing precision challenges during subsequent epitaxial growth and stacking operations
Solution Approach 2:
The patent introduces intermediary isolation layers and oxide structures between the n-type and p-type source/drain regions. These intermediary elements act as mediators that provide electrical insulation without requiring direct contact between opposite-polarity regions. The intermediary isolation structures simplify the manufacturing process by decoupling the positioning requirements of n-type and p-type transistors, reducing the overall manufacturing precision burden
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively isolates the source/drain regions, preventing parasitic leakage and enhancing the electrical performance of CFETs by ensuring high-quality electrical insulation and maintaining optimal device performance.
Implementation Method 1
isolation elements (which can be isolation plugs or a buried oxide portion of the substrate) can extend into the surface of a substrate
Implementation Method 2
there is a challenge in achieving effective electrical isolation between n-type and p-type epitaxial source/drain regions to prevent parasitic leakage through the substrate
Implementation Method 3
A liner dielectric is laterally adjacent the gate conductor
Implementation Method 4
epitaxial structures in 3D monolithic complementary field effect transistors (CFETs)
Data Source
AI summary
Integrated circuit structures include isolation elements extending into a substrate, and source/drain regions of a first transistor contacting the isolation elements. The isolation elements extend from the substrate to the source/drain regions of the first transistor. Isolation layers contact the source/drain regions of the first transistor, and source/drain regions of a second transistor also contact the isolation layers. Thus, the isolation layers are between the source/drain regions of the first transistor and the source/drain regions of the second transistor. Channel regions of the first transistor contact and extend between the source/drain regions of the first transistor, and channel regions of the second transistor contact and extend between the source/drain regions of the second transistor. A gate conductor surrounds sides of the channel region of the first transistor and the channel region of the second transistor.