Nanosheet Channel Post Replacement Gate Process for FETs
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Solution Overview
Problem
The manufacturing of nanosheet-based field effect transistors (FETs) is challenging due to their three-dimensional nature, leading to high parasitic capacitance and non-manufacturable processes, making it difficult to achieve scalable device structures.
Innovation Solution
A method involving the formation of dummy dielectric layers, nanosheets extending into source/drain regions, a high-k dielectric layer, and a conductive metal cap layer is used to fabricate FETs, with nanosheets grown in a (111) orientation and epitaxially formed to reduce parasitic capacitance and enhance manufacturability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If nanosheets are grown opening perpendicular to the seed opening, then III-V FET transistor structures can be manufactured, but the three-dimensional nature leads to high parasitic capacitance
Solution Approach 1:
The gate structure is segmented into multiple nanosheet channels stacked vertically, with each nanosheet separated by dielectric layers. This segmentation allows the gate to control multiple independent channels, reducing the parasitic capacitance at each individual channel while maintaining overall device performance
Solution Approach 2:
The patent transitions from planar gate structures to three-dimensional stacked nanosheet channels. By growing nanosheets in a vertical orientation perpendicular to the substrate, the device achieves better gate control and reduced parasitic capacitance through the additional vertical dimension
2Manufacturing precision
If conventional nanosheet manufacturing processes are used, then nanosheet structures can be formed, but the processes are non-manufacturable and difficult to scale
Solution Approach 1:
Seed structures are formed in advance on the substrate before nanosheet growth. These pre-formed seeds provide controlled nucleation sites that enable subsequent epitaxial growth to proceed uniformly across the wafer, making the process manufacturable and scalable
Solution Approach 2:
The patent replaces difficult mechanical nanosheet manipulation with epitaxial growth processes. By using vapor-phase epitaxy to grow nanosheets from seed structures, the manufacturing process becomes more controllable, repeatable, and suitable for high-volume production
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of FETs with reduced parasitic capacitance and improved manufacturability, facilitating the development of scalable III-V FET transistor structures with enhanced performance.
Implementation Method 1
One or more nanosheets of active transistor channels alternating between the plurality of dummy dielectric layers are formed extending at least part way into the plurality of source/drain regions
Data Source
AI summary
Device and method for fabricating a field effect transistor (FET) include forming plurality of dummy dielectric layers separated by a corresponding plurality of source/drain regions overlying a substrate. One or more nanosheets of active transistor channels alternating between the plurality of dummy dielectric layers are formed extending at least part way into the plurality of source/drain regions. A high-k dielectric layer is formed about and overlying the source/drain regions and portions of the one or more nanosheets not covered by the plurality of dummy dielectric layers. A conductive metal cap layer is formed overlying the high-k dielectric layer.