Nanosheet Channel Layout With Uneven Sheet Counts for Current Control
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Solution Overview
Problem
Current semiconductor devices face challenges in improving element performance and reliability, particularly in scaling technologies and suppressing short channel effects.
Innovation Solution
The semiconductor device incorporates a lower pattern with first and second channel patterns, each with a distinct number of sheet patterns, and includes gate structures with varying thicknesses of gate capping patterns to enhance performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi gate transistor with three-dimensional channel is used, then scaling is easily performed and current control capability is improved, but device complexity increases
Solution Approach 1:
The channel region is divided into multiple segments along the first direction, with each segment having a different number of sheet patterns. This segmentation allows independent optimization of each channel segment, enabling scaling while maintaining manageable complexity through modular design.
Solution Approach 2:
Different channel segments are configured with different numbers of sheet patterns according to their specific performance requirements. This local quality approach allows current control capability to be optimized in specific regions without uniformly increasing complexity across the entire device.
2Area of stationary object
If gate length is not increased, then device area is reduced, but current control capability may be insufficient
Solution Approach 1:
The invention transitions from controlling current through gate length (one dimension) to controlling current through the number of sheet patterns in the vertical direction (another dimension). This allows current control capability to be improved without increasing gate length, thereby reducing device area.
3Productivity
If different numbers of sheet patterns are used in different channel patterns, then current control capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The lower pattern is formed first as a common foundation for all channel segments. This preliminary action establishes a unified reference structure that simplifies subsequent formation of different sheet pattern configurations, thereby reducing manufacturing precision requirements.
Solution Approach 2:
The lower pattern serves as a template or copy base that is replicated across different channel segments. This copying approach ensures consistency in the foundation structure while allowing variations in sheet patterns, making manufacturing more precise and manageable.
4Reliability
If gate capping patterns with different thicknesses are used, then reliability is enhanced, but device complexity increases
Solution Approach 1:
Gate capping patterns are configured with different thicknesses in different regions according to specific reliability requirements. This local quality approach enhances reliability where needed without uniformly increasing complexity across the entire device structure.
Data Source
AI summary
A semiconductor device that includes a lower pattern extending in a first direction, a first channel pattern on the lower pattern, and includes a plurality of first sheet patterns, a second channel pattern on the lower pattern, includes a plurality of second sheet patterns and spaced apart from the first channel pattern, a first gate structure which extends around the first sheet pattern, and includes a first gate electrode and a first gate insulating film, a second gate structure which extends around the second sheet pattern, and includes a second gate electrode and a second gate insulating film, a first gate capping pattern and a second gate capping pattern. The number of first sheet patterns is different from the number of second sheet patterns, and a thickness of the first gate capping pattern is different from a thickness of the second gate capping pattern.