Nanosheet Transistor Channel Widening Through Sidewall Epitaxy

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Solution Overview

Problem

The challenge in semiconductor manufacturing is to maintain or increase the effective channel width of nanostructure transistors to enhance current conductivity without compromising the integrity of the transistor structure, as the channel width often decreases during processing, affecting performance.

Innovation Solution

A method involving a hard mask structure for patterning semiconductor layers, followed by an epitaxial growth process to increase the channel width by forming semiconductor layers on the exposed sides of the channels, ensuring the channels exceed the initial mask width, thereby enhancing the effective channel width.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If standard photolithography patterning is used to define channel width, then manufacturing precision is achieved, but the effective channel width decreases during subsequent processing steps

Engineering Contradiction:
Improvechannel width definitionVSAvoideffective channel width
Core Design Contradiction:
Manufacturing precisionVSLength of moving object

Solution Approach 1:

The patent applies preliminary action by forming an epitaxial semiconductor layer on the channels before final patterning steps. This epitaxial layer is grown to exceed the hard mask width, ensuring that even after processing losses, the effective channel width meets design requirements. The preliminary epitaxial growth compensates for anticipated width reduction in subsequent steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the physical and chemical parameters of the channel structure by performing epitaxial growth under controlled conditions. By adjusting growth temperature, pressure, and precursor flow rates, the semiconductor layer is grown with precise thickness and compositional control, enabling the channel width to exceed the initial mask dimensions while maintaining crystalline quality.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If channel width is increased to enhance current conductivity, then electrical performance improves, but device area and manufacturing complexity increase

Engineering Contradiction:
Improvecurrent conductivityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces mechanical patterning limitations with chemical epitaxial growth to achieve precise channel width control. Instead of relying solely on photolithography resolution and hard mask dimensions, the channel width is defined by controlled semiconductor layer growth, which offers superior dimensional control and eliminates the need for multiple patterning cycles.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent applies local quality by performing selective epitaxial growth only on the channel regions defined by the hard mask structure. The semiconductor layer is grown locally on the exposed substrate or sacrificial layer areas, ensuring that width enhancement occurs precisely where needed without affecting adjacent device structures or increasing overall device footprint.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in increased current conductivity in the on-state of the transistor, improving overall transistor performance and electronic device efficiency.

Implementation Method 1

an epitaxial growth process to increase the channel width by forming semiconductor layers on the exposed sides of the channels

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20250261393A1Method and device to increase nanosheet device width
Publication Date: 2025.08.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250261393A1 patent drawing
  • US20250261393A1 patent drawing
  • US20250261393A1 patent drawing

AI summary

A transistor includes a plurality of stacked channels. The stacked channels are initially patterned in accordance with a hard mask structure positioned above the stacked channels. Source/drain regions are then formed via a first epitaxial growth process such that the stacked channels extend in a first lateral direction between the source/drain regions. A second epitaxial growth process is then performed to increase the effective width of the channels by forming epitaxial semiconductor layers on side surfaces of the channels. After formation of the epitaxial semiconductor layers, the width of the channels in a second lateral direction transverse to the first lateral direction is greater than a width of the hard mask structure.