Nanosheet Transistor Channels via Epitaxy for Higher Width Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional techniques face limitations in scaling down semiconductor devices, such as FETs, due to challenges in increasing effective width and capacitance without increasing nanosheet stack height or epitaxial source/drain region volume, which affects performance and density in integrated circuits.
Innovation Solution
The method involves forming nanosheet transistor structures by epitaxially growing channel layers around sacrificial semiconductor layers, trimming mandrel channel portions to reduce height, and growing epitaxial channel layers around them, effectively doubling the number of channels without increasing stack height, thereby enhancing effective width and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional scaling techniques are used to increase effective width and capacitance, then device performance improves, but nanosheet stack height and epitaxial source/drain region volume must increase
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet stacks with gate-all-around configuration. By stacking multiple thin channel layers vertically and surrounding them with gates on all sides, the effective channel width increases without proportionally increasing the footprint area, while maintaining controlled source/drain volumes through epitaxial growth
Solution Approach 2:
The gate structures completely surround the nanosheet channels in a nested configuration, with gates positioned above, below, and on the lateral sides of each channel layer. This gate-all-around architecture provides maximum electrostatic control while achieving high effective width through vertical stacking rather than lateral expansion
2Quantity of substance
If nanosheet stack height is increased to improve performance, then effective width increases, but manufacturing complexity and device variability increase
Solution Approach 1:
The channel structure is segmented into multiple thin individual nanosheet layers stacked vertically, with each layer providing a portion of the total effective width. This segmentation allows better electrostatic control compared to a single thick channel, reduces variability, and enables precise thickness control through epitaxial growth processes
Solution Approach 2:
The patent controls the thickness, composition, and doping parameters of each nanosheet layer through epitaxial growth to optimize device performance. By precisely controlling these parameters during fabrication, the process achieves high effective width while maintaining manufacturing control and reducing variability
3Productivity
If more channel layers are stacked to increase density, then performance improves, but maintaining uniform epitaxial source/drain regions becomes more difficult
Solution Approach 1:
Sacrificial mandrel structures are temporarily inserted during the epitaxial growth process to define and protect the source/drain regions. These mandrels are later removed, leaving precisely formed epitaxial source/drain regions that uniformly connect to all stacked channel layers without requiring complex direct patterning
Solution Approach 2:
The sacrificial mandrel structures are pre-positioned before epitaxial growth to establish the geometry and positioning of the source/drain regions. This preliminary action ensures uniform epitaxial region formation across multiple stacked channels, simplifying the fabrication of high-density multi-layer structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased performance and density in integrated circuits by doubling the number of nanosheet channels without increasing stack height, improving effective capacitance and maintaining constant external resistance.
Implementation Method 1
techniques for forming semiconductor structures by epitaxially growing channel layers around sacrificial semiconductor layers
Data Source
AI summary
A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of epitaxial source/drain regions connected to the plurality of channel layers. The plurality of channel layers are connected to the plurality of epitaxial source/drain regions via a plurality of epitaxial extension regions. Respective pairs of adjacent channel layers of the plurality of channel layers are connected to a given one of the plurality of epitaxial source/drain regions via respective ones of the plurality of epitaxial extension regions.