Nanosheet CMOS Device Gradient Doping and Stacked Structure
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Solution Overview
Problem
Existing semiconductor devices face limitations in carrier mobility and power performance due to short-channel effects and complex manufacturing processes, which are not adequately addressed by current FinFET technologies.
Innovation Solution
A three-dimensional stacked gate-all-around nanosheet complementary inverter with junctionless transistors and a gradient channel doping profile is developed, featuring P-type and N-type semiconductor channels with varying doping concentrations and cross-sectional widths, allowing for improved hole and electron mobility, and reduced resistance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET technology is used to improve circuit control and reduce leakage current, then device performance is improved, but short-channel effects become more serious and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar FinFET structures to three-dimensional nanosheet structures with gate-all-around configuration. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sides), providing superior electrostatic control and reducing short-channel effects while maintaining manufacturability through established semiconductor processing techniques.
Solution Approach 2:
The gate structure completely surrounds and encapsulates the nanosheet channel, creating a nested configuration where the gate wraps around the channel in three dimensions. This gate-all-around structure provides enhanced control over the channel current and improves device performance by eliminating short-channel effects through complete gate coverage.
2Productivity
If channel length is shortened to improve device integration, then productivity increases, but short-channel effects worsen
Solution Approach 1:
The patent employs three-dimensional nanosheet channels with gate-all-around structures, transitioning from two-dimensional planar control to three-dimensional electrostatic control. This enables effective channel control even at reduced lengths, allowing higher device integration while maintaining reliability by suppressing short-channel effects through the enhanced gate control geometry.
3Ease of manufacture
If uniform doping concentration is used in the channel, then manufacturing simplicity is maintained, but carrier mobility is limited
Solution Approach 1:
The patent implements gradient doping where the doping concentration varies spatially within the channel, being highest at the surface and decreasing toward the center. This local variation in doping quality optimizes carrier mobility by reducing scattering effects at the channel interface while maintaining adequate doping for electrical control, thereby improving device performance without excessive manufacturing complexity.
Data Source
AI summary
This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a subtract; a P-type semiconductor channel and an N-type semiconductor channel, suspended on the subtract; a gate dielectric layer, wrapped around the P-type semiconductor channel and the N-type semiconductor channel; a gate electrode layer, wrapped around the gate dielectric layer; a P-type source region and a P-type drain region, connected to two ends of the P-type semiconductor channel respectively; an N-type source region and an N-type drain region, connected to two ends of the N-type semiconductor channel respectively; wherein the doping concentration at the surface of the P-type semiconductor channel is the highest, then decreases from the surface to the center region, the doping concentration at the surface of the N-type semiconductor channel is the highest, then decreases from the surface to the center region, and a cross-sectional width of the P-type semiconductor channel is greater than that of the N-type semiconductor channel. The present invention has ability to realize multi-layer staking under unit area, and reducing the length of the channel effectively so as to reduce channel effect and improve carrying capacity and integration level of the device.