Nanosheet CMOS Inner Spacer Layout for Leakage and FEOL Capacitance
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Solution Overview
Problem
Conventional nano-sheet-based transistors suffer from junction leakages in sub-channel regions and high capacitance at the front end of line (FEOL), which affect device performance.
Innovation Solution
The implementation of vertically-stacked horizontally-oriented multi-channel transistors with epitaxial source/drain features, where the sub-channel region is filled with epitaxial layers having reduced charge carrier mobility to minimize leakage current and capacitance, and the use of a gate structure that wraps around the channel layers to enhance control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional nano-sheet-based transistors are used, then gate control is improved and short-channel effects are reduced, but junction leakages occur in sub-channel regions and high capacitance appears at FEOL
Solution Approach 1:
The patent applies local quality by implementing asymmetric inner spacers with different widths at different locations within the source/drain regions. Specifically, the first inner spacer has a first width and the second inner spacer has a second width that is different from the first width. This local variation in spacer dimensions allows optimization of gate control in certain regions while minimizing junction leakage in sub-channel regions, thereby resolving the contradiction between improving gate control and reducing harmful leakage effects.
2Reliability
If conventional nano-sheet-based transistors are used, then gate control is improved, but high capacitance appears at the front end of line (FEOL)
Solution Approach 1:
The patent implements local quality through asymmetric inner spacers where the first inner spacer has a first width and the second inner spacer has a second width different from the first width. This localized variation in spacer dimensions optimizes the electrical characteristics at different positions, specifically reducing capacitance at the FEOL while preserving effective gate control, thus resolving the contradiction between these two parameters.
3Productivity
If geometry size is decreased through scaling down, then production efficiency increases and costs are lowered, but complexity of IC processing increases
Solution Approach 1:
The patent applies asymmetry by configuring inner spacers with different widths at different locations (first inner spacer with first width, second inner spacer with second width). This asymmetric structure enables effective gate control and reduced leakage in scaled-down devices without requiring proportionally increased processing complexity, as the asymmetric spacer formation can be integrated into existing fabrication processes through selective deposition and etching steps.
Data Source
AI summary
A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.