Nanosheet Gate-All-Around Contact Layout for Reliable Source/Drain Links
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Solution Overview
Problem
The challenge in semiconductor devices is to enhance the reliability of electrical connections between the source/drain region and the lower source/drain contact in multi-gate transistors, particularly in multi-bridge channel field effect transistors (MBCFETs), to improve scalability and suppress short channel effects.
Innovation Solution
The semiconductor device incorporates a lower interlayer insulating layer with an insulating pattern and a gate electrode surrounding semiconductor nanosheets, featuring a lower source/drain contact and insulating liner layers to ensure reliable electrical connections, utilizing materials like silicon germanium (SiGe) and specific dielectric materials for improved conductivity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-gate transistor with three-dimensional channel is used to improve current control capability and suppress short channel effects, then device performance is improved, but the reliability of electrical connection between source/drain region and lower source/drain contact deteriorates
Solution Approach 1:
The lower source/drain contact is divided into two separate contacts: a first lower source/drain contact connected to the first source/drain region, and a second lower source/drain contact connected to the second source/drain region. This segmentation isolates the electrical connection paths, preventing interference between adjacent regions and improving connection reliability in the complex multi-gate structure.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the lower source/drain contacts and the source/drain regions. This insulating layer provides electrical isolation and mechanical support, ensuring stable electrical connections while accommodating the three-dimensional channel structure of the multi-gate transistor.
2Productivity
If scaling is increased to improve integration density, then more devices can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The lower source/drain contacts extend in the vertical direction beneath the source/drain regions, utilizing the depth dimension to establish electrical connections. This vertical extension provides larger contact area and improved connection reliability without increasing lateral footprint, enabling higher integration density while maintaining manufacturability.
Solution Approach 2:
The insulating layer is formed beforehand to define the connection regions before the lower source/drain contacts are formed. This preliminary action establishes precise alignment references that guide subsequent fabrication steps, reducing alignment precision requirements as scaling increases.
Data Source
AI summary
A semiconductor device is provided that includes a lower interlayer insulating layer, an insulating pattern on the lower interlayer insulating layer and extending in a first horizontal direction, a plurality of semiconductor nanosheets stacked on an upper surface of the insulating pattern, a gate electrode that extends in a second horizontal direction and surrounding the plurality of semiconductor nanosheets, a first source/drain region disposed on the insulating pattern at a first side of the gate electrode, a second source/drain region disposed on the insulating pattern at a second side of the gate electrode opposite to the first side of the gate electrode, a lower source/drain contact that penetrates the lower interlayer insulating layer and the insulating pattern, the lower source/drain contact electrically connected to the second source/drain region, and a first insulating liner layer in contact with both sidewalls of the first portion of the lower source/drain contact.