Multi-Stack Nanosheet Transistor Isolation With Dam Structures

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Solution Overview

Problem

The existing manufacturing process for high-density transistors is not suitable for nanosheet transistors, leading to potential electrical short circuits between multi-stack transistor structures.

Innovation Solution

A dam structure is formed between adjacent rows and columns of multi-stack transistor structures during manufacturing to electrically isolate them, preventing short circuits by controlling the spread of etchants and ensuring proper contact formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the existing manufacturing process for high-density transistors is used, then device density is improved, but electrical short circuits occur between multi-stack transistor structures

Engineering Contradiction:
Improvedevice densityVSAvoidelectrical short circuit prevention
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent divides the continuous array of multi-stack transistor structures into isolated units by forming dam structures between adjacent stacks. This segmentation prevents electrical short circuits while maintaining high device density by allowing close proximity arrangement of individual transistor stacks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dam structure acts as an intermediary element positioned between adjacent multi-stack transistor structures. This intermediate feature provides electrical isolation and prevents harmful electrical interactions while enabling the dense packing of transistor stacks that would otherwise be impossible.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If dam structures are formed to isolate multi-stack transistor structures, then electrical short circuit prevention is improved, but manufacturing process complexity increases

Engineering Contradiction:
Improveelectrical short circuit preventionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dam structures are formed at an early stage in the manufacturing process, before subsequent processing steps. This preliminary action simplifies the overall manufacturing complexity by establishing the isolation framework early, allowing later steps to proceed without additional isolation concerns.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dam structure serves multiple functions: it provides electrical isolation between transistor stacks, defines the boundaries for source/drain region formation, and serves as a reference for subsequent patterning steps. This multi-functionality reduces the need for separate structures for each function, thereby simplifying the overall manufacturing process.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If dam structures are formed early in manufacturing, then contact formation precision is improved, but device density may be reduced

Engineering Contradiction:
Improvecontact formation precisionVSAvoiddevice density
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The dam structures are positioned with precise local spacing to provide just enough isolation while maximizing the remaining space for transistor stacks. This local optimization of spacing allows contact formation precision to be improved without significantly compromising overall device density.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11742345B2Method of forming an array of multi-stack nanosheet structures having a dam structure isolating multi-stack transistors
Publication Date: 2023.08.29 SAMSUNG ELECTRONICS CO LTD
  • US11742345B2 patent drawing
  • US11742345B2 patent drawing
  • US11742345B2 patent drawing

AI summary

An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.