Nanosheet Transistor Dipole Layer for Threshold and Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistor dimensions continue to scale down, further improvements are needed in nanosheet FETs to maintain effective gate control and reduce short-channel effects, while also addressing challenges in fabrication and design for higher device density and lower costs.
Innovation Solution
The process involves forming a stack of semiconductor layers with alternating first and second semiconductor layers, patterning fin structures, forming insulating material, recessing the insulating material to create isolation regions, and depositing a dipole layer and capping layer to enhance threshold voltage tuning and carrier mobility, with a gate electrode layer surrounding the nanosheet channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then productivity and production efficiency are improved, but gate control capability deteriorates and short-channel effects increase
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet channels with gate-all-around configuration. The gate electrode completely surrounds the nanosheet channel in three dimensions, providing superior electrostatic control and reducing short-channel effects while maintaining scaled dimensions. This dimensional change allows the gate to control the channel from all directions (top, bottom, and sides), effectively suppressing leakage currents and maintaining gate control capability at smaller dimensions.
Solution Approach 2:
The patent employs composite material structures including alternating layers of semiconductor materials (e.g., Si/SiGe) to form the nanosheet channels and surrounding layers. These composite structures provide different functionalities: Si layers form the active channel with good carrier mobility, while SiGe layers provide strain engineering to enhance carrier mobility and serve as sacrificial layers during fabrication. The dipole layer (e.g., GeO2) introduces electric field effects to further modulate carrier mobility. This composite approach enables simultaneous optimization of gate control, carrier mobility, and fabrication processability.
2Reliability
If complex fabrication processes are used to improve nanosheet FET performance, then device performance is improved, but manufacturing complexity and costs increase
Solution Approach 1:
The patent incorporates preliminary actions in the fabrication sequence by forming the dipole layer and capping layer structures before final gate electrode deposition. The dipole layer (e.g., GeO2) is formed through controlled oxidation of Ge-containing layers, creating a layer that will later provide electric field effects for mobility enhancement. The capping layer is formed beforehand to protect underlying structures during subsequent processing steps. These preliminary structures are integrated into the overall fabrication flow rather than added as separate post-processing steps, managing complexity through planned integration.
Solution Approach 2:
The patent uses intermediary layers and materials to simplify the fabrication process. The SiGe sacrificial layers serve as intermediaries that define the nanosheet channel regions and are selectively removed to release the nanosheets, eliminating the need for complex release processes. The dipole layer acts as an intermediary between the gate electrode and the channel, providing electric field control and mobility enhancement without requiring direct modification of the channel structure. These intermediary elements mediate between fabrication constraints and performance requirements, simplifying the overall process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves threshold voltage tuning capability and carrier mobility, reducing germanium loss and increasing throughput, enabling more efficient manufacturing of nanosheet FETs with enhanced performance and reduced costs.
Implementation Method 1
depositing a dipole layer and capping layer to enhance threshold voltage tuning and carrier mobility
Implementation Method 2
The capping layer reduces germanium loss of the p-dipole layer by at least 80%
Data Source
AI summary
A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.