Nanosheet Gate Stack With Dipole Dielectric for Threshold Voltage Tuning
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Solution Overview
Problem
In nanosheet devices, the thick gate interfacial layer in the I/O area limits the space between channel semiconductor layers, preventing the formation of a work function metal layer and merging high-k dielectric layers, which hinders the achievement of the desired threshold voltage and degrades device performance.
Innovation Solution
The channel semiconductor layers in the I/O area are trimmed to be thinner than those in the core area, enlarging the space between them, allowing for the formation of a work function metal layer and enabling dipole processing of high-k dielectric layers, thereby facilitating the formation of metal gate structures and adjusting the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick gate interfacial layer is used in the I/O area, then gate control is improved, but the space between channel semiconductor layers is reduced, preventing work function metal layer formation
Solution Approach 1:
The patent applies different interfacial layer thicknesses to different regions: a first (thinner) interfacial layer thickness in the core area and a second (thicker) interfacial layer thickness in the I/O area. This local differentiation allows the I/O area to achieve improved gate control while the core area maintains sufficient space for work function metal layer formation between channel semiconductor layers.
2Productivity
If the space between channel semiconductor layers is limited, then device scaling is achieved, but high-k dielectric layers merge and work function metal cannot be formed
Solution Approach 1:
The patent implements region-specific interfacial layer thicknesses that enable different functional requirements to be met simultaneously: the core area uses a thinner interfacial layer to maintain compact spacing for device scaling, while the I/O area uses a thicker interfacial layer to provide sufficient space for work function metal layer formation and prevent high-k dielectric layer merging.
3Device complexity
If work function metal layer formation is prevented, then fabrication complexity is reduced, but threshold voltage control is lost
Solution Approach 1:
The patent enables work function metal layer formation selectively in the core area by using a thinner interfacial layer thickness, while the I/O area uses a thicker interfacial layer that prevents work function metal formation. This local differentiation preserves threshold voltage control where needed (core area) while avoiding unnecessary complexity where it is not required (I/O area).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach mitigates the merging of high-k dielectric layers, allows for the formation of metal gate structures, and enables the achievement of the desired threshold voltage, improving the performance of nanosheet devices by providing sufficient space for gate electrode formation and dipole processing.
Implementation Method 1
a dipole gate dielectric layer around the interfacial layer and over the gate dielectric layer
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.