Gate-All-Around Transistor Dipole Oxide for Threshold Voltage Separation

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Solution Overview

Problem

In gate all around transistors, it is challenging to achieve transistors with different selected threshold voltages without introducing unwanted variations in threshold voltages.

Innovation Solution

Incorporating dipole layers at the interfacial dielectric layer on semiconductor nanosheets, formed in a way that reduces unwanted variations in threshold voltages, allowing for transistors with distinct threshold voltages by adjusting the dipole effect on the gate electrode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If dipole layers are incorporated to achieve different threshold voltages, then threshold voltage control precision is improved, but device complexity increases

Engineering Contradiction:
Improvethreshold voltage control precisionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by incorporating dipole layers selectively at specific interfaces (e.g., between gate dielectric and channel) rather than uniformly throughout the device. This localized modification allows precise threshold voltage tuning in specific transistor regions while maintaining simplicity in other areas, resolving the contradiction between control precision and device complexity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent utilizes parameter changes by modifying the dipole moment, concentration, or orientation of dipole layers to achieve different threshold voltage values. By changing these physical parameters of the dipole layer, the invention enables continuous threshold voltage adjustment without fundamentally altering the device structure, thus improving control precision while managing complexity

Inventive Principle:
Principle #35Parameter changes

2Reliability

If dipole layers are incorporated to achieve different threshold voltages, then device performance is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedevice performanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by incorporating dipole layers during the gate dielectric formation process or as a separate preparatory step before transistor fabrication. This advance incorporation simplifies subsequent manufacturing steps and ensures consistent threshold voltage control, improving device performance while managing manufacturing complexity through process integration

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dipole layer serves as an intermediary between the gate dielectric and the channel, mediating the electric field distribution to achieve desired threshold voltages. This intermediary layer provides a simple and effective mechanism for threshold voltage control that can be integrated into existing manufacturing processes, improving performance without excessive manufacturing complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach increases device performance and yield by reliably achieving different threshold voltages in transistors, ensuring no unwanted dipole layer formation in unintended transistors, thus maintaining consistent and improved transistor performance.

Implementation Method 1

The incorporation of dipole layers at the interfacial dielectric layer on semiconductor nanosheets allows for the achievement of different threshold voltages by reducing unwanted variations

Methodology Applied
Scientific EffectDipole effect:

Data Source

PatentUS20240145470A1Integrated circuit including dipole incorporation for threshold voltage tuning in transistors
Publication Date: 2024.05.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240145470A1 patent drawing
  • US20240145470A1 patent drawing
  • US20240145470A1 patent drawing

AI summary

A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.