Nanosheet Source/Drain Doping Structure for Leakage Barrier Control
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing leakage current and improving reliability due to limitations in source/drain region doping and gate electrode design, particularly in multi-gate transistors where scaling and short channel effects are prominent.
Innovation Solution
The semiconductor device incorporates a specific structure with a doped active pattern, nanosheets, and a gate insulation layer, where the lower source/drain region is either doped with impurities of the same conductivity type as the active pattern or remains undoped, and the upper source/drain region is doped with a different conductivity type, enhancing the energy barrier and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the lower source/drain region is doped with impurities of the same conductivity type as the active pattern, then the energy barrier is increased and leakage current is reduced, but the manufacturing complexity increases due to multiple doping steps
Solution Approach 1:
The source/drain region is divided into two distinct segments: a lower source/drain region doped with impurities of the first conductivity type (same as active pattern) and an upper source/drain region doped with impurities of the second conductivity type (opposite to active pattern). This segmentation allows each region to perform its specific function - the lower region creates an energy barrier to reduce leakage current, while the upper region provides standard source/drain functionality.
Solution Approach 2:
Different doping configurations are applied to different vertical levels of the source/drain region. The lower portion has one doping characteristic (first conductivity type) while the upper portion has another (second conductivity type). This local quality variation enables the lower region to specifically address leakage current through energy barrier formation, while the upper region maintains compatibility with the active pattern's conductivity type.
2Reliability
If the gate insulation layer is positioned to contact both lower and upper source/drain regions, then the energy barrier effectiveness is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The gate insulation layer is formed to contact both the lower source/drain region and the upper source/drain region before final device assembly. This preliminary configuration ensures that the energy barrier is established early in the manufacturing process, and subsequent steps can proceed without compromising the barrier's effectiveness. The gate electrode is then positioned relative to this pre-configured insulation layer structure.
3Reliability
If the upper source/drain region is doped with impurities of different conductivity type than the active pattern, then the leakage current is reduced through enhanced energy barrier, but the device complexity increases
Solution Approach 1:
Instead of doping the upper source/drain region with the same conductivity type as the active pattern (conventional approach), this invention inverts the approach by doping it with the opposite conductivity type. This inversion creates an additional energy barrier at the interface between the upper source/drain region and the active pattern, effectively reducing leakage current through a mechanism opposite to the conventional single-type doping approach.
Data Source
AI summary
A semiconductor device includes an active pattern with a first impurity having a first conductivity, first and second nanosheets on the active pattern, a gate electrode on the active pattern and surrounding each of the first and second nanosheets, a lower source/drain region on the active pattern, an uppermost surface of the lower source/drain region being lower than a lower surface of the second nanosheet, and the lower source/drain region being doped with a second impurity having the first conductivity, an upper source/drain region on the lower source/drain region, the upper source/drain region being doped with a third impurity having a second conductivity different from the first conductivity, and a gate insulation layer between the gate electrode and the lower and upper source/drain regions, the gate insulation layer being in contact with each of the lower and upper source/drain regions.