Nanosheet Transistor Doping Layers for Threshold Voltage Control
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Solution Overview
Problem
Current semiconductor devices face challenges in effectively controlling the threshold voltage of PMOS and NMOS transistors, particularly in scaling integrated circuit density and managing short channel effects.
Innovation Solution
The implementation of doping layers made of silicon (Si) or silicon germanium (SiGe) with n-type or p-type doping materials on the surfaces of nanosheets in PMOS and NMOS transistors, respectively, to control the threshold voltage and improve current control capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor with three-dimensional channel is used, then scaling capability and current control capability are improved, but threshold voltage control becomes difficult
Solution Approach 1:
The patent applies local quality by forming doping layers at specific locations on the nanosheet surfaces. The doping layers are selectively formed on the front surface or side surfaces of the nanosheets, creating localized doped regions that precisely control threshold voltage without affecting the overall three-dimensional channel structure. This localized doping approach enables independent optimization of threshold voltage control while maintaining the scaling benefits of the multi-gate transistor architecture.
2Ease of manufacture
If gate length is not increased in multi-gate transistor, then scaling is easier, but short channel effect increases
Solution Approach 1:
The patent changes the electrical parameters of the channel region by introducing doping layers with controlled doping concentrations and types (n-type or p-type). This modifies the carrier concentration and threshold voltage in the channel, enabling effective suppression of short channel effects even when the gate length is scaled down. The doping layers create potential barriers that prevent drain-induced barrier lowering, thereby mitigating short channel effects without requiring increased gate length.
3Manufacturing precision
If doping layer is added to control threshold voltage, then threshold voltage control is improved, but device complexity increases
Solution Approach 1:
The patent merges the doping layer formation process with the existing nanosheet fabrication process. The doping layers are formed integrally with the nanosheet structure, combining multiple functions (threshold voltage control and channel formation) into a unified structure. This integration approach adds threshold voltage control capability while minimizing the increase in device complexity by utilizing the same fabrication工艺流程 for both the nanosheets and doping layers.
Data Source
AI summary
A semiconductor device may include a substrate, an active pattern extended in a first horizontal direction on the substrate, a plurality of nanosheets stacked and spaced apart from each other in a vertical direction on the active pattern, a gate electrode extended in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region on both sides of the plurality of nanosheets in the first horizontal direction on the active pattern, a gate insulating layer between the plurality of nanosheets and the gate electrode, and a doping layer between the plurality of nanosheets and the gate insulating layer, the doping layer including silicon (Si) or silicon germanium (SiGe) and doped with a doping material, at least a portion of the doping layer overlapping an uppermost nanosheet of the plurality of nanosheets in the first horizontal direction.