Nanosheet Gate-All-Around Doping Layout for Vt and Leakage Control
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Solution Overview
Problem
As semiconductor devices are scaled down, issues such as off-state current leakage and voltage threshold (Vt) shift due to anti-punch through (APT) doping diffusion during fabrication become significant concerns.
Innovation Solution
Integration of horizontal gate-all-around nanosheet transistors with controlled dopant implantation processes, including anti-punch through (APT) implantations and selective etching to form nanosheet channels, mitigates Vt shift and reduces leakage by enhancing dopant concentration profiles in source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimension is scaled down to increase functional density, then production efficiency and cost are improved, but off-state current leakage and voltage threshold shift occur due to APT doping diffusion
Solution Approach 1:
The patent applies local quality by creating a non-uniform dopant concentration profile within the channel region. Specifically, it forms a first dopant region with higher concentration near the source/drain junctions and a second dopant region with lower concentration toward the channel center. This spatial variation in dopant concentration locally optimizes each region: the high-concentration zones suppress leakage at critical interfaces while the low-concentration zone maintains channel conductivity, thereby resolving the contradiction between scaling down for productivity and preventing leakage for reliability.
Solution Approach 2:
The patent employs parameter changes by systematically varying dopant concentration as a function of position within the channel. The dopant concentration is engineered to decrease from the source/drain interfaces toward the channel middle, creating a graded profile. This parameter variation allows the device to achieve both low leakage (through high concentration at interfaces) and good on-state current (through low concentration in the channel bulk), thus resolving the scaling-induced contradiction between productivity gains and reliability maintenance.
2Stability of the object's composition
If APT doping is applied to prevent punch through, then device stability is improved, but voltage threshold shift occurs due to dopant diffusion
Solution Approach 1:
The patent applies segmentation by dividing the dopant distribution into distinct regions: a first dopant region with higher concentration near the source/drain junctions and a second dopant region with lower concentration toward the channel center. This segmentation allows the high-concentration zones to provide punch-through protection and stability while the low-concentration zone prevents excessive voltage threshold shift, thereby resolving the contradiction between device stability and voltage threshold control precision.
Solution Approach 2:
The patent employs preliminary anti-action by pre-configuring the dopant concentration profile to counteract the harmful effects of dopant diffusion. The graded profile is designed in advance to limit the extent of diffusion-induced voltage threshold shift while maintaining the stabilizing effect against punch-through. This preemptive design approach resolves the contradiction by anticipating and mitigating the voltage threshold shift problem before it occurs during device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates Vt shift and reduces leakage by optimizing dopant distribution, improving device performance and manufacturing efficiency in advanced semiconductor technologies.
Implementation Method 1
implanting first anti-punch through dopants into a substrate... implanting second anti-punch through dopants into the substrate
Implementation Method 2
anti-punch through (APT) doping diffusion during fabrication
Data Source
AI summary
A semiconductor device structure includes a first S/D feature over a first device region of a substrate, a plurality of first semiconductor layers over the first device region of the substrate, and each first semiconductor layer is in contact with the first source/drain feature, a first gate electrode layer surrounding a portion of each first semiconductor layer, and a first dielectric spacer contacting the first S/D feature, the first dielectric spacer disposed between and in contact with two first semiconductor layers of the plurality of the first semiconductor layers. The substrate comprises a first dopant region underneath the first S/D feature and a second dopant region underneath first gate electrode layer and radial outwardly of the first dopant region, the first dopant region comprising first dopants having a first conductivity type and a first dopant concentration and the second dopant region comprising the first dopants having a second dopant concentration less than the first dopant concentration.