Vertically Stacked Nanosheet E-Fuses for Multi-Bit Storage
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Solution Overview
Problem
Conventional semiconductor e-fuses are limited to single-bit storage, requiring a large footprint on chip surfaces and consuming significant power, making it challenging to scale beyond the 10 nm node and efficiently manage increasing data storage needs.
Innovation Solution
The formation of vertically stacked nanosheet e-fuses with tapered sidewalls, allowing for multiple-bit storage by varying fuse lengths and breakdown voltages, which reduces the chip surface area required and enables efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional single-bit e-fuses are used, then each fuse can store one bit of data, but a large footprint is required on chip surfaces
Solution Approach 1:
The patent transitions from planar single-bit e-fuses to vertically stacked multi-bit e-fuses, utilizing the third dimension (vertical stacking) to increase storage capacity without proportionally increasing chip footprint. Multiple e-fuse bits are stacked vertically within the same lateral footprint area
Solution Approach 2:
The patent combines multiple e-fuse bits into a single integrated structure with shared common anode and cathode regions. This merging approach allows multiple storage bits to coexist in a compact vertical stack, reducing the overall chip area required compared to separate single-bit fuses
2Quantity of substance
If conventional single-bit e-fuses are used, then each fuse structure is simple, but significant power is consumed
Solution Approach 1:
The patent combines multiple e-fuse bits into a single integrated structure with shared common anode and cathode regions. This merging approach allows multiple storage bits to coexist in a compact vertical stack, reducing the overall chip area required compared to separate single-bit fuses
3Manufacturing precision
If conventional planar e-fuse structures are used, then fabrication is straightforward, but scaling beyond 10 nm node is challenging
Solution Approach 1:
The patent transitions from planar single-bit e-fuses to vertically stacked multi-bit e-fuses, utilizing the third dimension (vertical stacking) to increase storage capacity without proportionally increasing chip footprint. Multiple e-fuse bits are stacked vertically within the same lateral footprint area
Solution Approach 2:
The patent segments the e-fuse structure into distinct vertical layers including alternating sacrificial and non-sacrificial nanosheet layers. This segmentation enables precise control over fuse characteristics and facilitates scaling to advanced technology nodes through controlled material removal and selective etching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased data storage capacity with a reduced chip footprint, optimizing power usage and preventing reverse engineering through a nonplanar memory structure.
Implementation Method 1
converting the second material to a resistive material
Implementation Method 2
removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate
Data Source
AI summary
A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate. The method further includes converting the second material to a resistive material. The layers that include the resistive material form one or more electrical fuses.