Nanosheet Extension Profiles and Air Spacers for FETs
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Solution Overview
Problem
Conventional semiconductor fabrication techniques face challenges in miniaturizing field-effect transistors (FETs) beyond atomic level scaling, particularly in optimizing nanosheet extension profiles to reduce parasitic capacitance and enhance performance in integrated circuit devices.
Innovation Solution
The method involves forming nanosheet stacks with alternating sacrificial and channel layers, creating vertical fins and indented sidewalls, and forming nanosheet extension regions that increase in thickness from the indented sidewalls to the vertical fins, accompanied by the deposition of inner spacers and air gaps using conformal processes to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional fabrication techniques are used for miniaturizing FETs, then atomic level scaling is achieved, but parasitic capacitance increases and performance deteriorates
Solution Approach 1:
The patent applies local quality by creating a non-uniform nanosheet extension profile where the nanosheet thickness varies along the extension region. The nanosheet is thinner near the gate and thicker toward the source/drain regions, optimizing the electrical characteristics locally in different regions to reduce parasitic capacitance while maintaining performance
Solution Approach 2:
The patent introduces a vertical dimension to the nanosheet extension profile by creating thickness variation through selective etching and deposition processes. This vertical/thickness dimension complements the horizontal length scaling, enabling performance optimization without further reducing the already minimal horizontal dimensions
2Reliability
If nanosheet extension regions are formed to reduce parasitic capacitance, then performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming sacrificial layers and mandrels before creating the final nanosheet extension structure. These preliminary structures guide the subsequent selective removal and deposition processes, enabling the complex non-uniform profile to be achieved through a sequence of simpler, more controllable fabrication steps
Solution Approach 2:
The patent uses sacrificial layers and mandrels as intermediary structures that facilitate the formation of the desired nanosheet extension profile. These intermediaries are temporarily introduced, used to define the extension geometry, and then removed or transformed, simplifying the overall manufacturing process by breaking down the complex formation into manageable stages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach optimizes the nanosheet extension profile, reduces parasitic capacitance, and enhances the starting source/drain epitaxial surface, leading to improved performance and density in integrated circuit devices.
Implementation Method 1
forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers
Data Source
AI summary
A method of forming a semiconductor structure includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating sacrificial and channel layers, the channel layers providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the nanosheet stack and a portion of the substrate, and forming indents in sidewalls of the sacrificial layers at sidewalls of the vertical fins. The method further includes forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins, the nanosheet extension regions increasing in thickness from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins. The method further includes forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.