Nanosheet FET Source/Drain Air-Gap Structure for Defect Control
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Solution Overview
Problem
As integrated circuit devices downscale, they face challenges in achieving both fast operation speed and high operational accuracy, with increased possibilities of process defects in nanosheet field-effect transistors, necessitating a new structure to enhance performance and reliability.
Innovation Solution
The integration of fin-type active areas with channel regions, gate lines, and source/drain regions, including semiconductor layers and air gaps, to stabilize and improve the performance of nanosheet field-effect transistors, with specific geometries and doping to optimize semiconductor layers and air gap placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated circuit devices are downscaled to increase integration density, then the degree of integration increases, but process defects in nanosheet field-effect transistors increase and reliability deteriorates
Solution Approach 1:
The source/drain region is segmented into multiple semiconductor layers (first, second, and third semiconductor layers) stacked vertically. This segmentation allows each layer to be independently optimized and formed through controlled epitaxial growth, reducing process defects while maintaining high integration density. The multi-layer structure enables better control over electrical properties and stress distribution compared to a monolithic structure.
Solution Approach 2:
Different semiconductor layers are introduced with specific materials and properties at different locations within the source/drain region. The first semiconductor layer contacts the channel region, the second layer is positioned intermediate, and the third layer is at the bottom contacting the fin-type active area. This local quality variation allows optimization of electrical characteristics at each interface while maintaining overall device reliability.
2Productivity
If integrated circuit devices are downscaled to increase integration density, then the degree of integration increases, but operational accuracy deteriorates
Solution Approach 1:
The channel region is segmented into multiple nanosheets stacked vertically, with gate lines surrounding each nanosheet. This segmentation into discrete nanosheet channels allows for better control of carrier transport and reduces variability in operational characteristics, thereby improving operational accuracy while maintaining high integration density through vertical stacking.
Solution Approach 2:
The device transitions from a planar structure to a three-dimensional vertically-stacked structure with multiple nanosheets and gate lines at different heights. This dimensional change enables independent control of each nanosheet channel, improving operational accuracy through better electrostatic control and reduced interference between adjacent channels.
3Productivity
If nanosheet field-effect transistors are used to increase integration, then the degree of integration increases, but process defects increase
Solution Approach 1:
The semiconductor layers are formed through controlled epitaxial growth processes before final device assembly. The first semiconductor layer is grown to contact the channel, followed by the second layer, and finally the third layer at the bottom. This preliminary formation of layered structures with controlled composition and thickness reduces manufacturing variability and process defects.
Solution Approach 2:
The epitaxial growth parameters (temperature, pressure, gas flow rates, precursor ratios) are precisely controlled and optimized for each semiconductor layer formation. By changing and optimizing these parameters, the manufacturing process achieves better layer uniformity, reduced defects, and improved reproducibility, thereby reducing process defect rates while maintaining high integration density.
Data Source
AI summary
An integrated circuit device includes a plurality of fin-type active areas extending in a first horizontal direction on a substrate, a plurality of channel regions respectively on the plurality of fin-type active areas, a plurality of gate lines surrounding the plurality of channel regions on the plurality of fin-type active areas and extending in a second horizontal direction that crosses the first horizontal direction, and a plurality of source/drain regions respectively at positions adjacent to the plurality of gate lines on the plurality of fin-type active areas and respectively in contact with the plurality of channel regions, and the plurality of source/drain regions respectively include a plurality of semiconductor layers and at least one air gap located therein.