Nanosheet FET Vertical Blocker Fin for Selective Gate Etching
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Solution Overview
Problem
Nanosheet transistor devices face manufacturing challenges due to the complexity of forming CMOS cells with pFET and nFET gates, where etching the pFET work function material from the nFET region can lead to inefficient or non-functional pFET devices due to the flow of etchant.
Innovation Solution
The introduction of vertical blocking fins on the nFET stack of nanosheet channel structures, made of the same material as the channel region, slows etchant flow and protects the pFET gate during etching, while also increasing the effective channel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching is performed to remove pFET work function material from the nFET region, then the nFET gate can be formed, but the etchant may flow into the pFET region and cause unwanted etching of the pFET gate
Solution Approach 1:
A vertical blocker fin is introduced as an intermediary structure between the nFET and pFET regions. This fin acts as a physical barrier that intercepts and blocks the etchant flow, preventing it from reaching the pFET gate. The blocker fin is strategically positioned to serve as a mediator that allows the necessary etching process to occur while protecting the adjacent pFET structure from damage.
Solution Approach 2:
The vertical blocker fin is formed in advance before the critical etching step. By establishing this protective structure beforehand, the system prepares a defense mechanism that will prevent harmful etchant flow during the subsequent etching process. This preliminary action ensures that when the etching occurs, the pFET gate is already protected by the pre-positioned blocker fin.
2Productivity
If multiple nanosheet channels are stacked to increase channel exposure, then the effective channel width increases, but the complexity of forming separate pFET and nFET stacks increases
Solution Approach 1:
The nanosheet stack is segmented into distinct regions: nFET nanosheet channels, pFET nanosheet channels, and blocker fins. This segmentation allows each component to be optimized independently while maintaining overall device performance. The nFET and pFET regions can be processed differently, and the blocker fins can be strategically placed without requiring complete redesign of the entire stack structure.
Solution Approach 2:
The vertical blocker fin serves multiple functions simultaneously: it blocks etchant flow to protect the pFET gate, it increases the effective channel width of the nFET device, and it provides structural support within the nanosheet stack. This multi-functionality reduces the need for additional separate structures, thereby managing complexity while maintaining productivity.
Data Source
AI summary
A FET channel includes a stack of silicon nanosheets. The silicon nanosheets are oriented parallel to a planar portion of the FET in which the FET channel is formed. The FET channel also includes a vertical blocker fin. The vertical blocker fin is attached to at least one nanosheet in the stack of nanosheets.