Nanosheet FET Source/Drain Blocking Structure for Leakage Control
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Solution Overview
Problem
As integrated circuit devices shrink in size, there is a need to increase the degree of integration of field-effect transistors on substrates, particularly in horizontal nanosheet field-effect transistors (hNSFETs), where existing designs face challenges in enhancing performance and reliability due to manufacturing defects and leakage current issues.
Innovation Solution
The integration of a fin-type active area with a device isolation layer, a gate structure crossing the fin-type active area, and source/drain areas featuring a double-layered blocking structure, including an outer Si1-xGex layer, an inner Si layer, and a main body layer, which applies strain to nanosheets and protects the main body layer from external attacks during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of integrated circuit devices is decreased to increase degree of integration, then more transistors can be packed on substrate, but manufacturing defects and leakage current issues worsen
Solution Approach 1:
The source/drain area is segmented into multiple functional layers: outer blocking layer (Si1-xGex), inner blocking layer (Si), and main body layer. This segmentation allows each layer to perform specific functions - the outer and inner blocking layers prevent leakage and protect against defects, while the main body layer provides the primary conduction path, thus resolving the contradiction between high integration and reliability.
Solution Approach 2:
The source/drain structure uses composite materials combining Si1-xGex and Si layers. The Si1-xGex outer blocking layer provides strain engineering benefits for carrier mobility while the Si inner blocking layer offers superior electrical isolation. This composite approach enables simultaneous achievement of high integration density and improved reliability through material property optimization.
2Productivity
If horizontal nanosheet field effect transistors are used to increase integration density, then more devices fit on substrate, but performance enhancement is limited by leakage current
Solution Approach 1:
The harmful leakage current path is extracted and blocked by introducing separate blocking layers (outer and inner) that are specifically designed to prevent current leakage. The inner blocking layer of Si material specifically targets and eliminates leakage paths in the hNSFET structure, allowing high integration density to be achieved without the performance-limiting leakage current.
3Ease of manufacture
If source/drain area is simplified without blocking layers, then manufacturing is easier, but reliability against defects and leakage current deteriorates
Solution Approach 1:
The blocking layers are formed as preliminary structures during the source/drain fabrication process. The outer blocking layer (Si1-xGex) and inner blocking layer (Si) are created before the main body layer, establishing protective barriers in advance that prevent leakage and defect propagation. This preliminary action approach maintains manufacturing feasibility while significantly improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances carrier mobility in nanosheets, improves the reliability of the integrated circuit device by preventing defects and leakage currents, and ensures stable performance in horizontal nanosheet field-effect transistors.
Implementation Method 1
a main body layer, and wherein the main body layer applies strain to the nanosheets
Data Source
AI summary
An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1−xGex layer, where x≠0, and the inner blocking layer including a Si layer.