Nanosheet FET Bottom Dielectric Isolation and High-k Gate
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Solution Overview
Problem
Fork nanosheet FET devices face challenges such as unwanted diffusion of elements during high-temperature processing, leading to poor interface quality and degraded electron mobility, and difficulties in forming bottom dielectric isolation due to oxidation of sacrificial nanosheets, which complicates their fabrication.
Innovation Solution
The method involves forming semiconductor FET devices with bottom dielectric isolation and high-κ first, where sacrificial layers are selectively removed and replaced with a dielectric material before shallow trench isolation, avoiding oxidation and high-temperature processing issues, and using a replacement metal gate process to maintain gate integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high temperature processing is used during conventional fabrication, then the nanosheet channels can be formed, but unwanted diffusion of elements occurs leading to poor interface quality and degraded electron mobility
Solution Approach 1:
The gate dielectric is deposited on the nanosheet channels before high-temperature source/drain processing. This preliminary action protects the nanosheet interfaces from element diffusion during subsequent high-temperature steps, maintaining interface quality while allowing necessary thermal processing to occur.
Solution Approach 2:
The gate dielectric serves as an intermediary protective layer between the nanosheet channels and the high-temperature processing environment. It prevents unwanted element diffusion into the nanosheet interfaces while permitting the high-temperature steps needed for source/drain formation.
2Reliability
If bottom dielectric isolation is formed by removing bottom nanosheets, then leakage is suppressed and parasitic capacitance is reduced, but oxidation of bottom nanosheets during processing makes removal difficult
Solution Approach 1:
The bottom nanosheets are removed and replaced with dielectric material before oxidation-prone processing steps. This preliminary removal prevents oxidation of the bottom nanosheets, making the isolation formation process easier while achieving effective leakage suppression and parasitic capacitance reduction.
Solution Approach 2:
The fabrication process is segmented into distinct stages: first removing bottom nanosheets to form isolation regions, then proceeding with gate and source/drain formation. This segmentation allows bottom dielectric isolation to be established before subsequent processing, avoiding oxidation issues and simplifying manufacturing.
3Area of stationary object
If spacing between NFET and PFET is reduced for area scaling, then device area is reduced, but fabrication challenges increase with fork nanosheet design
Solution Approach 1:
A single gate dielectric deposition step forms the gate dielectric for both NFET and PFET devices in the fork nanosheet structure. This multi-functional approach achieves area scaling by sharing common processing steps and materials, reducing fabrication complexity despite the reduced spacing between complementary devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses leakage, reduces parasitic capacitance, and maintains low thermal budgets, ensuring better interface quality and electron mobility by avoiding Ge diffusion and simplifying the removal of sacrificial nanosheets, thus enhancing the fabrication process of fork nanosheet FET devices.
Implementation Method 1
gates include a gate dielectric that wraps around the active layers but is absent from sidewalls of the inner spacers
Implementation Method 2
bottom dielectric isolation is important to suppress leakage and to reduce parasitic capacitance
Data Source
AI summary
Semiconductor FET devices with bottom dielectric isolation and high-κ first are provided. In one aspect, a semiconductor FET device includes: a substrate; at least one device stack including active layers oriented horizontally one on top of another on the substrate; source and drains alongside the active layers; and gates, offset from the source and drains by inner spacers, surrounding a portion of each of the active layers, wherein the gates include a gate dielectric that wraps around the active layers but is absent from sidewalls of the inner spacers. A method of forming a semiconductor FET device is also provided.