Nano-Sheet FET Source/Drain Buffer Structure for Leakage Control
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Solution Overview
Problem
As the size of integrated circuit devices decreases, the degree of integration of field-effect transistors (FETs) increases, leading to higher process defects in nano-sheet FET manufacturing, which necessitates a structure that minimizes defects and improves performance and reliability.
Innovation Solution
A semiconductor device with a fin active region, device isolation layer, gate structure, and nano-sheet structure, where the nano-sheets are spaced apart vertically, and source/drain regions include a buffer layer, inner impurity layer, and central impurity layer, with the buffer layer filling indentations and contacting the inner impurity layer, and the nano-sheets are surrounded by a metal gate in a gate all around (GAA) structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of FETs is increased to reduce device size, then more FETs can be placed on a substrate, but process defects increase
Solution Approach 1:
The source/drain region is segmented into multiple functional layers: buffer layer, inner impurity layer, and central impurity layer. Each layer serves a specific function in preventing defects and ensuring proper electrical characteristics, thereby maintaining reliability while supporting high integration
Solution Approach 2:
The buffer layer is formed in advance to fill indentations between nano-sheets before the impurity layers are deposited. This preliminary action prevents short circuits and leakage current by establishing proper electrical isolation and contact structures beforehand
2Productivity
If nano-sheets are stacked vertically to increase integration, then device density improves, but short circuits and leakage occur
Solution Approach 1:
The buffer layer acts as an intermediary structure between the fin active region and the impurity layers, filling the indentations created by vertically stacked nano-sheets. This intermediary structure prevents direct contact that would cause short circuits while allowing proper current flow through the impurity layers
Solution Approach 2:
The source/drain region is given different local qualities through its layered structure: the buffer layer provides electrical isolation and mechanical support in the indentation areas, while the impurity layers provide conductive paths where needed, creating locally optimized properties to prevent both short circuits and leakage
3Reliability
If buffer layer fills indentations between nano-sheets, then short circuits are prevented, but device structure becomes more complex
Solution Approach 1:
The buffer layer performs multiple functions simultaneously: it fills the indentations between vertically stacked nano-sheets, provides electrical isolation to prevent short circuits, creates proper contact surfaces for the impurity layers, and maintains mechanical structural integrity. This multi-functionality justifies the added structural complexity by delivering multiple reliability benefits from a single layer
Data Source
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AI summary
A semiconductor device (100), including a fin active region (FA); a device isolation layer (114) covering two sidewalls of the fin active region (FA) on a substrate (102); a gate structure (GST); a nano-sheet structure (NSS) including a plurality of nano-sheets (N1, N2, N3); and source/drain regions (130) disposed on the fin active region (FA) and adjacent to the gate structure (GST), wherein each source/drain region (130) of the source/drain regions includes a buffer layer (132), an inner impurity layer (134), and a central impurity layer (136) which are sequentially stacked, wherein the buffer layer (132) fills a first indentation between two vertically-adjacent nano-sheets (N1, N2) and a second indentation between the top surface of the fin active region (FA) and a nano-sheet (N3), and wherein the plurality of nano-sheets (N1, N2, N3) contact side surfaces of the inner impurity layer (134).