Si and Non-Si Nanosheet FET Co-Integration for Leakage Control
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Solution Overview
Problem
As integrated circuits shrink, the lateral spacing between vertical fin-based field-effect transistors becomes too small, leading to operational issues, and stacked nanosheet FETs are developed to increase effective conduction width, but they face challenges with band-to-band tunneling-induced leakage current, especially in non-Si nanosheet FETs which have higher channel carrier mobility but also higher leakage current.
Innovation Solution
The integration of both Si and non-Si nanosheet FETs in integrated circuits, where non-Si nanosheets with less than 30% Si define critical speed paths with a barrier height limiting band-to-band tunneling-induced current, and Si nanosheets with more than 30% Si define non-critical speed paths, optimizing leakage current and performance through distinct gate stack configurations and thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If non-Si nanosheet FETs are used to increase channel carrier mobility, then device speed is improved, but band-to-band tunneling-induced leakage current increases
Solution Approach 1:
The patent applies local quality by using different nanosheet compositions in different circuit regions: non-Si nanosheets (less than 30% Si) are placed in critical speed paths where high carrier mobility is needed, while Si nanosheets (more than 30% Si) are used in non-critical speed paths where low leakage current is the priority. This spatial differentiation allows each region to optimize for its specific performance requirement.
Solution Approach 2:
The patent segments the integrated circuit into distinct functional regions based on speed requirements. Critical speed paths are separated from non-critical speed paths, allowing independent optimization of nanosheet composition in each segment. This segmentation enables the circuit to achieve both high performance in critical paths and low power consumption in non-critical paths.
2Quantity of substance
If lateral spacing between vertical fins is reduced to increase device density, then integration density is improved, but device operation reliability deteriorates
Solution Approach 1:
The patent transitions from two-dimensional planar FinFET structures to three-dimensional stacked nanosheet FETs. By stacking multiple nanosheets vertically, the effective conduction width is increased without increasing the lateral footprint, thereby maintaining high device density while avoiding the reliability issues associated with reduced lateral spacing between fins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This co-integration approach enhances performance by reducing propagation delays in critical speed paths while minimizing power consumption due to low band-to-band tunneling leakage current, achieving both high performance and low power consumption in integrated circuits.
Implementation Method 1
a barrier height from source to channel below a threshold value that is sufficient to limit the band-to-band tunneling induced current to substantially less than the conventional sub-threshold leakage current
Data Source
AI summary
An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.