Differential Interfacial Layer Thickness in Nanosheet FETs
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Solution Overview
Problem
Current techniques for forming multiple work function nanosheet field-effect transistors face challenges in achieving differential interfacial layer thickness, which is essential for creating multiple threshold voltages without the need for additional patterning steps, especially in nanosheet devices where space between sheets is limited.
Innovation Solution
The technique involves forming semiconductor structures with differential interfacial layer thickness by using varying capping metals in different regions, allowing controlled interfacial layer scavenging during anneal, thereby achieving two levels of effective work function for negative and positive channel field-effect transistors without increasing electrical thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform interfacial layer thickness is used for all nanosheet channels, then manufacturing process is simplified, but multiple threshold voltages cannot be achieved
Solution Approach 1:
The patent applies local quality by creating different interfacial layer thicknesses in different regions of the nanosheet device. Specifically, a first interfacial layer thickness is formed in first regions containing first nanosheet channels, while a second interfacial layer thickness is formed in second regions containing second nanosheet channels. This regional differentiation enables multiple threshold voltages to be achieved without complicating the overall manufacturing process, as the thickness variation is achieved through localized processing rather than complete process redesign.
2Adaptability or versatility
If additional patterning steps are added to create differential interfacial layer thickness, then multiple threshold voltages can be achieved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming the interfacial layer with the desired thickness variation before the main nanosheet formation process. The differential interfacial layer thickness is established in advance on the substrate, and subsequent processing steps follow the standard nanosheet fabrication flow without requiring additional patterning. This preliminary preparation eliminates the need for extra manufacturing steps while still achieving multiple threshold voltage control.
3Reliability
If interfacial layer thickness is increased to improve interface quality, then device reliability improves, but device thickness increases
Solution Approach 1:
The patent applies parameter changes by optimizing the interfacial layer thickness to achieve the minimum required value that provides sufficient interface quality and device reliability. Rather than using uniformly thick interfacial layers, the invention employs differential thicknesses where each region's interfacial layer is sized appropriately for its specific requirements. This parameter optimization ensures that device thickness is minimized while maintaining necessary interface quality through controlled thickness variation across different regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively sets multiple threshold voltages for nanosheet FETs by controlling interfacial layer thickness, avoiding the need for additional patterning and maintaining minimal device thickness, thus enhancing mobility and reducing variability.
Implementation Method 1
performing an anneal to selectively thin the interfacial layers surrounding the second set of two or more nanosheet channels for the second NFET and the fourth set of two or more nanosheet channels for the second PFET
Data Source
AI summary
A semiconductor structure includes a substrate, an isolation layer disposed over the substrate, a plurality of nanosheet channels, interfacial layers surrounding each of the nanosheet channels, and dielectric layers surrounding each of the interfacial layers. The plurality of nanosheet channels includes first and second sets of two or more nanosheet channels for first and second NFETs and third and fourth sets of two or more nanosheet channels for first and second PFETs. The interfacial layers surrounding the first and third sets of nanosheet channels for the first NFET and the first PFET have a first thickness, and interfacial layers surrounding the second and fourth sets of nanosheets channels for the second NFET and the second PFET have a second thickness smaller than the first thickness. The first NFET has a higher threshold voltage than the second NFET, and the first PFET has a lower threshold voltage than the second PFET.