Nanosheet FET Dipole Layer Structure for Short-Channel Control
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Solution Overview
Problem
As transistor dimensions are scaled down, further improvements are needed in nanosheet FETs to enhance device performance and reduce short-channel effects while maintaining effective gate control and increasing device density.
Innovation Solution
The manufacturing process involves forming a stack of semiconductor layers with alternating materials of different etch selectivity and oxidation rates, creating fin structures, and using a sacrificial gate structure with spacers to define nanosheet channels, followed by the deposition of a dipole layer and capping layer to tune threshold voltage and improve carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then productivity and cost are improved, but short-channel effects worsen and gate control deteriorates
Solution Approach 1:
The patent transitions from planar transistor geometry to three-dimensional nanosheet structures with gate-all-around configuration. The channel is formed as a thin sheet surrounded by the gate electrode on all sides (top, bottom, and sidewalls), effectively adding vertical dimension to gate control. This dimensional change enables continued scaling while maintaining electrostatic control and reducing short-channel effects.
Solution Approach 2:
The gate electrode completely surrounds the nanosheet channel in a nested configuration, with the gate wrapping around the channel from all directions. This nested gate-all-around structure provides 360-degree control of the channel, maximizing electrostatic influence and improving threshold voltage control compared to conventional planar gates.
2Productivity
If transistor dimensions are scaled down to increase device density, then productivity is improved, but short-channel effects increase
Solution Approach 1:
The patent employs three-dimensional nanosheet channel structures with thickness in the nanometer range, transitioning from two-dimensional planar channels to three-dimensional confined structures. This dimensional change enhances gate electrostatic control over the channel, effectively suppressing short-channel effects that arise from lateral dimension scaling.
Solution Approach 2:
The patent uses alternating layers of different semiconductor materials (e.g., Si/SiGe) to form the nanosheet structure. The composite material approach allows selective etching of sacrificial layers while maintaining the nanosheet channel integrity, enabling precise control of channel dimensions and properties to mitigate short-channel effects.
3Ease of manufacture
If conventional planar transistor structures are used, then manufacturing is simpler, but gate control and performance are insufficient at scaled dimensions
Solution Approach 1:
The patent segments the channel into multiple thin nanosheets stacked vertically, each surrounded by its own gate electrode. This segmentation approach transforms the conventional single planar channel into multiple three-dimensional channels, improving gate control and performance while maintaining compatibility with scaled fabrication processes.
Solution Approach 2:
The patent introduces sacrificial intermediary layers (e.g., SiGe layers) that are temporarily present during fabrication to define the nanosheet channel regions. These intermediary layers are selectively removed to release the nanosheets and form the gate-all-around structure, enabling complex three-dimensional geometry through simplified sequential processing steps.
Data Source
AI summary
A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.