Nanosheet FET Source/Drain Tapering for Complete Epitaxy
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving optimal channel resistance and epitaxy growth profiles for nanosheet FETs, as existing methods often result in increased channel resistance due to incomplete epitaxy growth and uneven geometries, affecting device performance and yield.
Innovation Solution
The solution involves a specific pulsing scheme during the etching process, using a combination of source and bias powers to control ion movement and achieve a tapered profile for the source/drain regions, which allows for more efficient epitaxial growth and reduced channel resistance by ensuring complete filling of the epitaxial features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used, then the etching process is simple and fast, but the source/drain regions have uneven geometry leading to incomplete epitaxy growth and increased channel resistance
Solution Approach 1:
The patent applies periodic pulsing of RF bias power during the etching process to create a tapered profile in source/drain regions. The RF bias power is pulsed between 0 and 100-500W at frequencies of 10-1000Hz, creating periodic ion bombardment that facilitates conformal epitaxial growth while maintaining a controlled tapered geometry. This periodic action resolves the contradiction by introducing controlled complexity in the time domain to achieve superior spatial uniformity in the source/drain profile.
Solution Approach 2:
The patent dynamically adjusts the RF bias power during the etching process, transitioning from static to dynamic control. By varying the bias power in real-time during etching, the process creates a tapered profile that optimizes subsequent epitaxial growth. This dynamic approach allows the system to adapt the etching rate and ion bombardment intensity throughout the process, achieving uniform source/drain geometry while managing process complexity through automated control.
2Reliability
If the source/drain regions have a tapered profile, then epitaxial growth is improved and channel resistance is reduced, but the etching process requires complex pulsing schemes
Solution Approach 1:
The periodic pulsing of RF bias power creates the tapered profile necessary for reliable epitaxial growth. By cycling the bias power between 0 and 100-500W at controlled frequencies, the process achieves consistent source/drain geometry that ensures complete epitaxial filling and reduces channel resistance. This periodic control mechanism reliably produces the desired tapered profile, improving device yield despite the increased process complexity.
Solution Approach 2:
The patent changes multiple etching parameters simultaneously, including RF bias power (100-500W), frequency (13.56MHz), and pulsing frequency (10-1000Hz), to achieve the tapered profile. By optimizing these parameters together, the process creates ideal conditions for subsequent epitaxial growth, ensuring complete filling of source/drain regions and reducing channel resistance. This multi-parameter approach improves reliability by creating a robust process window that consistently produces high-quality devices.
3Productivity
If nanosheet FETs are scaled down, then device density is increased, but channel resistance increases due to incomplete epitaxy growth
Solution Approach 1:
The patent performs preliminary etching to create a tapered profile in the source/drain regions before epitaxial growth. This pre-shaping of the source/drain regions ensures that subsequent epitaxial growth can proceed uniformly and completely fill the tapered spaces, even in scaled-down nanosheet FETs. By preparing the geometry in advance, the process prevents incomplete epitaxy growth that would otherwise increase channel resistance in high-density devices.
Solution Approach 2:
The patent applies local quality by creating a non-uniform tapered profile specifically in the source/drain regions while maintaining uniform nanosheet channels. The tapered source/drain regions have gradually varying geometry that is optimized for epitaxial growth, while the channel regions maintain their precise dimensions. This localized geometric optimization ensures complete epitaxial filling in source/drain regions without compromising channel quality, enabling high device density with low channel resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach leads to improved channel resistance and device performance by preventing voids and ensuring complete epitaxial growth, thereby enhancing the conductivity and yield of nanosheet FETs.
Implementation Method 1
perform a plasma etch to remove a portion of the second semiconductor layers
Implementation Method 2
a pulsing scheme is applied during a plasma etch process
Data Source
AI summary
A method of forming a nanosheet FET is provided. A plurality of first and second semiconductor layers are alternately formed on a substrate. The first and second semiconductor layers are patterned into a plurality of stacks of semiconductor layers separate from each other by a space along a direction. Each stack of semiconductor layers has a cross-sectional view along the direction gradually widening towards the substrate. An epitaxial feature is formed in each of the spaces. The patterned second semiconductor layers are then removed from each of the stacks of semiconductor layers.