Nanosheet FET Gate Extension Layout for Contact Spacing
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Solution Overview
Problem
In nanosheet field effect transistors (FETs), the close proximity of gate contacts to source/drain contacts can lead to manufacturing inconsistencies causing shorts and increased capacitance, which affect device performance.
Innovation Solution
The implementation of a gate extension over the source-drain region adjacent to the gate allows the gate contact to be placed over the source-drain region instead of the traditional gate region, creating additional space between contacts and reducing the risk of shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate contacts are routed near source/drain contacts in traditional gate regions, then the device structure is compact, but manufacturing inconsistencies cause shorts and increased capacitance
Solution Approach 1:
The gate is extended from the traditional horizontal gate region into the vertical space above the source/drain region. This three-dimensional gate extension allows the gate contact to be positioned above the source/drain contact rather than adjacent to it in the same plane, effectively using the vertical dimension to resolve the contact proximity issue and reduce capacitance while maintaining compact footprint.
2Area of stationary object
If gate contacts are placed close to source/drain contacts, then the layout is compact, but capacitance between contacts increases
Solution Approach 1:
By extending the gate vertically above the source/drain region, the gate contact can be positioned in the vertical dimension rather than being constrained to the horizontal plane. This spatial separation reduces the overlapping area between gate and source/drain contacts, thereby decreasing parasitic capacitance while preserving compact device footprint.
3Ease of manufacture
If gate contacts are routed near source/drain contacts, then routing is simplified, but manufacturing precision requirements increase due to short risks
Solution Approach 1:
The gate extension creates a vertical separation between the gate contact and source/drain contacts, moving them to different vertical levels. This dimensional separation provides larger lateral spacing between contacts in the routing plane, reducing the risk of shorts and lowering manufacturing precision requirements while maintaining routing simplicity.
Data Source
AI summary
A nanosheet field effect transistor (FET) comprises a diffusion region and a gate. The diffusion region connects to a backside power delivery network. The diffusion region is beneath the gate. The gate is in a first gate region. The gate comprises a first gate extension region that extends over the diffusion region.